CSU ROM and FSBL send power up/down requests to PMU via the
PWR_UP/PWR_DN request register in PMU_GLOBAL. This module
handles these requests and routes them to respective ROM handlers
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
Add new events and supporting functions to handle legacy
ROM power up and power down requests that are initiated
using PMU GLOBAL registers.
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
Add DAP event handler to PMU Firmware as a new user module and pass on
the handling to respective ROM Handlers.When a DAP wake arrives,
PMU should ACK the DAP Wake using its local registers.
PMU ROM has handlers for these and we will re-use these handlers here.
This module is enabled only if ENABLE_PM is not defined to avoid conflict
with the PM module
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
This patch removes the gap in serial numbering of PM API ids
between PM_SET_MAX_LATENCY and PM_RESET_ASSERT defined in
pm_defs.h
Signed-off-by: Rohit Fule <rohitf@xilinx.com>
Tested-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
This patch removes clock related PM API ids defined in pm_defs.h
under sw_services and reassigns ids in serial order.
Signed-off-by: Rohit Fule <rohitf@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
Execution state of A53 (64-bit/32-bit) is now determined based on __aarch64__ value
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
This patch adds support for FSBL running in A53 32-bit mode and
also supports handing off to A53 32-bit applications from FSBL.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
As per specification.
- Always enable enhanced framing mode.
- Declare training pattern 3 support if core is DP v1.2.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
If an interrupt occurs without a user defined callback, don't invoke the
function.
Otherwise, unexpected behavior will be seen due to running code from 0x0 (NULL).
Prior to this, it was the responsibility of the user to ensure all callbacks for
interrupts were set.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
The interrupt mask and interrupt cause registers are independent. The interrupt
handler has been modified to ignore interrupts that have been masked out.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Added new interrupts, callbacks, and macros related to HDCP (High-bandwidth
Digital Content Protection).
Added new interrupts, callbacks, and macros for an unplug event.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Fixed compilation warnings when using:
-Wall -Wextra
No need for ">=0" assertions on arguments that are of unsigned type.
Removed unused variables.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
The naming of this example is better described as SST with DP159
functionality.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
The programming sequence required by the DP159 retimer has been
added.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Set the reset value for the timer upon initialization.
Use the timer ID as an argument for consistency with the other
device IDs.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Using the DP159 solution, 8 ms needs to be used as the AUX training
interval.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
RX initialization is not dependent on PLL and reset checks.
- Training will not be initiated until the RX is ready.
The clock is transmitted only once the cable is connected.
- This means that the CPLLs will never lock if no cable is plugged
in resulting in DP RX core initialization time out.
Moved core and interrupt mask enables towards end of function.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Example has been modified to support both Zynq PL eFuse and
Ultrascale eFuse. Added GPIO pins and channels to access
Master Jtag through GPIO and RSA key hash, AES's CRC value
input macros are also added.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
As GpioPs and Timers are different for Ultrascale
all the calls related to Gpio and timers are saperated
by ifdefinitions.
Added new jtag function to access efuse of Ultrascale.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
To add ultrascale's efuse functionality added GPIO pins
and GPIO channels to access master JTAG, Fpga_Flag to tell
the FPGA series, AES CRC check flag and AES CRC value, RSA key
hash to program and RSA key hash read back and control and
secure parameters in PL instance and modified IR length
macro ZYNQ_TAP_IR_LENGTH to TAP_IR_LENGTH as IR length is same for both
Zynq and Ultrasale.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
Removed redundant code by adding common API for clock
calculations.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
Modified tcl for adding macro in xparameters.h based on the
processor.As support is being added for Ultrascale and hence
supported processors are a9 and microblaze too, removed
supported peripherals option in mld.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
-Added logic to fix vdma ip alignement issues with different bit
width at axis and aximm interface at all supported pixel/clk
and color depth combinations
-Moved stream (input/output) validation logic scattered around
in different blocks to a central location
-Added API to report subsystem configuration status
-Code cleanup and changed relevant prints to dbg print
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
4 Samples/Clock phase calculation logic works on 64bit entities.
However a 32bit variable was used that caused wrong phase
information to be generated. Updated relevant variables to 64b
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
- Code cleanup to remove interrupt handler registration.
Subsystem does not have interrupts
- Updated sub-core init routines to load default filter
coefficients for scaler and chroma resamplers
- Added layer 2 registers for chroma resamplers
- Updated VDMA Read/Write interface to work with color depth
instead of Bytes/Pixel
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
- IP updated to add multiple pixel/clk support.
- Added default filter coefficient table for 6/8/10/12 taps
- Added API to load default coefficients or allow user to load
externally defined coefficients
- Peformed code cleanup to remove coefficient generation logic
(scaler to use fixed coefficients)
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
-Added filter coefficient table for 4/6/8/10 taps.
-Added API to load the default coefficients
-Added API to allow user to load coefficients
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
- IP updated to add multiple pixel/clk support.
- Added default filter coefficient table for 6/8/10/12 taps
- Added API to load default coefficients or allow user to load
externally defined coefficients
- Peformed code cleanup to remove coefficient generation logic
(scaler to use fixed coefficients)
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
-Added filter coefficient table for 4/6/8/10 taps.
-Added API to load the default coefficients
-Added API to allow user to load coefficients
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
IP updated to add multiple pixels per clock support resulting in
API changes in driver.
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
This patch adds copyright info to HLS generated mdd file
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
