Commit graph

288 commits

Author SHA1 Message Date
Jyotheeswar Reddy
a414510d6a PMUFW: EM: Add new error management framework
A framework to enable handling of HW errors reported via ERROR_1 and ERROR_2
registers in PMU GLOBAL space is provided. User can choose to register an
action for an error by using the provided API. An API is provided to enable
Error reporting via PSERR pin.

Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
2015-08-07 18:37:18 +05:30
Jyotheeswar Reddy
63266cf2b9 PMUFW: Scheduler: Fix interval comparision logic
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
2015-08-07 18:36:51 +05:30
Jyotheeswar Reddy
54d744d315 PMUFW: Core: Add API to remove a task from scheduler
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
2015-08-07 18:36:15 +05:30
Jyotheeswar Reddy
40cd4f3229 PMUFW: Mod: Add CSU lock down request to legacy module
Register for secure lock-down request from CSU and
call the corresponding ROM handler when this event occurs

Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
2015-08-07 18:35:33 +05:30
Jyotheeswar Reddy
7968c6a661 PMUFW: Interrupts: Add CSU secure lock down interrupt handler
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
2015-08-07 18:35:12 +05:30
Jyotheeswar Reddy
f5b94e4ea2 PMUFW: Events: Add CSU secure lock down request events
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
2015-08-07 18:34:27 +05:30
Jyotheeswar Reddy
b7d22226d9 PMUFW: Interrupts: Fix Event IDs in debug message
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
2015-08-07 18:33:57 +05:30
Jyotheeswar Reddy
6b0ba64eda PMUFW: MOD: Add new module for legacy power request handling
CSU ROM and FSBL send power up/down requests to PMU via the
PWR_UP/PWR_DN request register in PMU_GLOBAL. This module
handles these requests and routes them to respective ROM handlers

Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
2015-08-07 18:33:11 +05:30
Jyotheeswar Reddy
bc66b745b7 PMUFW: Events: Add REQ_PWRUP and REQ_PWRDN events
Add new events and supporting functions to handle legacy
ROM power up and power down requests that are initiated
using PMU GLOBAL registers.

Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
2015-08-07 18:32:51 +05:30
Jyotheeswar Reddy
6fe99fac43 PMUFW: MOD: Add DAP Wake Module
Add DAP event handler to PMU Firmware as a new user module and pass on
the handling to respective ROM Handlers.When a DAP wake arrives,
PMU should ACK the DAP Wake using its local registers.
PMU ROM has handlers for these and we will re-use these handlers here.
This module is enabled only if ENABLE_PM is not defined to avoid conflict
with the PM module

Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
2015-08-07 18:23:31 +05:30
Suneel Garapati
9a13c33ea1 lib: sw_apps: freertos support for latest bsp
change to freertos821_xilinx version

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Acked-by: Anirudha Sarangi   <anirudh@xilinx.com>
2015-08-07 16:10:39 +05:30
Rohit Fule
6c9a54d19b PMUFW: PM: Modified serial ordering of PM API ids
This patch removes the gap in serial numbering of PM API ids
between PM_SET_MAX_LATENCY and PM_RESET_ASSERT defined in
pm_defs.h

Signed-off-by: Rohit Fule <rohitf@xilinx.com>
Tested-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
2015-08-07 16:03:33 +05:30
Rohit Fule
652be149c6 sw_services:xilpm: Modified serial ordering of PM_API ids
This patch removes clock related PM API ids defined in pm_defs.h
under sw_services and reassigns ids in serial order.

Signed-off-by: Rohit Fule <rohitf@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
2015-08-07 16:01:41 +05:30
Sarat Chand Savitala
61bd977834 sw_apps:zynqmp_fsbl: Corrected the logic used to determinte A53 Execution state
Execution state of A53 (64-bit/32-bit) is now determined based on __aarch64__ value

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
2015-08-07 16:01:05 +05:30
Sarat Chand Savitala
84204047c7 sw_apps:zynqmp_fsbl: Added A53 32-bit support in FSBL
This patch adds support for FSBL running in A53 32-bit mode and
also supports handing off to A53 32-bit applications from FSBL.

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
2015-08-06 15:33:14 +05:30
VNSL Durga
7ca1fb1844 xilskey: Modified example and input.h files
Example has been modified to support both Zynq PL eFuse and
Ultrascale eFuse. Added GPIO pins and channels to access
Master Jtag through GPIO and RSA key hash, AES's CRC value
input macros are also added.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-08-05 21:05:52 +05:30
VNSL Durga
02ccf03a94 xilskey: Added ultrascale efuse functionality
Added macros and functions required for accessing
Ultrascale's eFuse

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-08-05 21:05:39 +05:30
VNSL Durga
0b14b181ba xillskey: Added new functions
As GpioPs and Timers are different for Ultrascale
all the calls related to Gpio and timers are saperated
by ifdefinitions.
Added new jtag function to access efuse of Ultrascale.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-08-05 21:05:24 +05:30
VNSL Durga
365de9549f xilskey: Modified PL instance.
To add ultrascale's efuse functionality added GPIO pins
and GPIO channels to access master JTAG, Fpga_Flag to tell
the FPGA series, AES CRC check flag and AES CRC value, RSA key
hash to program and RSA key hash read back and control and
secure parameters in PL instance and modified IR length
macro ZYNQ_TAP_IR_LENGTH to TAP_IR_LENGTH as IR length is same for both
Zynq and Ultrasale.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-08-05 21:05:07 +05:30
VNSL Durga
00e045e760 xilskey:Added API for clk calculations.
Removed redundant code by adding common API for clock
calculations.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-08-05 21:04:48 +05:30
VNSL Durga
e2ccad3c90 xilskey: Modified xilskey_efuse_example
Modified macro name of efuse PS XSK_EFUSEPL_RSA_KEY_HASH_STRING_SIZE
to XSK_EFUSEPS_RSA_KEY_HASH_STRING_SIZE.
Added missing goto.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-08-05 21:04:35 +05:30
VNSL Durga
841227f998 xilskey: Added new version v3_0
Modified tcl for adding macro in xparameters.h based on the
processor.As support is being added for Ultrascale and hence
supported processors are a9 and microblaze too, removed
supported peripherals option in mld.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-08-05 21:03:24 +05:30
Bhavik Ameta
d27a264328 sw_services:xilsecure: Changed RSA API error codes
RSA sign verification error codes combined into XST_FAILURE.

Signed-off-by: Bhavik Ameta <bameta@xilinx.com>
Acked-by: Sarat Chand Savitala <saratcha@xilinx.com>
2015-08-04 18:05:10 +05:30
Bhavik Ameta
976c6455ad sw_services:xilsecure: Pointer warnings fixed
Changed u64 casts to UINTPTR, to fix the warnings.

Signed-off-by: Bhavik Ameta <bameta@xilinx.com>
Acked-by: Sarat Chand Savitala <saratcha@xilinx.com>
2015-08-04 18:05:01 +05:30
Bhavik Ameta
2491b4d9a2 sw_services:xilsecure: R5 build failure fixed
Removed individual checks for compilers from Makefile.These were causing build failure.

Signed-off-by: Bhavik Ameta <bameta@xilinx.com>
Acked-by: Sarat Chand Savitala <saratcha@xilinx.com>
2015-08-04 18:04:29 +05:30
Nava kishore Manne
7a47ffd9e8 Removed executable file permission from source code files.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Acked-by: Anirudha Sarangi   <anirudh@xilinx.com>
2015-08-03 18:32:57 +05:30
Sarat Chand Savitala
4968e7c610 sw_apps:zynqmp_fsbl: Updated watchdog code for JTAG bootmode
As in JTAG bootmode, watchdog is not initialized, avoided stopping of
watchdog in JTAG bootmode.

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
2015-08-03 14:55:49 +05:30
Sarat Chand Savitala
dff2a597f9 sw_apps:zynqmp_fsbl: Added watchdog support
This patch adds System Watchdog Timer support

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
2015-08-02 21:27:53 +05:30
P L Sai Krishna
09cd729c86 xilffs: Used --create option for armcc compiler.
This patch use --create option for armcc compiler
instead of rc option.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-07-31 16:56:24 +05:30
Kinjal Pravinbhai Patel
60c693e0fe bsp: added support for 32bit bsp for A53
This patch modifies standalone bsp tcl to generate 32bit/64bit
a53 bsp by keeping compiler check in the tcl to copy the
appropriate source file while generating standalone bsp

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi   <anirudh@xilinx.com>
2015-07-31 16:56:22 +05:30
Sarat Chand Savitala
e1dd360db8 sw_apps:zynqmp_fsbl: Code cleanup involving emulation platforms
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
2015-07-31 16:56:20 +05:30
RamyaSree
8dc4f9e7fd sw_apps: zynqmp_fsbl: Modified bus width in dummy phase.
This patch modifies the buswidth in dummy phase as
in data phase.

Signed-off-by: RamyaSree <rdarapun@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-07-31 16:56:19 +05:30
RamyaSree
8e402be829 sw_apps: zynqmp_fsbl: enabled cache for qspipsu boot.
This patch enables cache for qspipsu boot.

Signed-off-by: RamyaSree <rdarapun@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-07-31 16:56:19 +05:30
RamyaSree
6f67bc7850 sw_apps: zynqmp_fsbl: added Tx/Rx Flags in qspi message format
This patch added Tx/Rx flags in qspi message format
according to qspipsu driver changes.

Signed-off-by: RamyaSree <rdarapun@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-07-31 16:56:18 +05:30
Soren Brinkmann
731fcf06db xilsecure: Fix make rules
When building xilsecure with '-rR' as arguments to make causes this error:
  Compiling Xilsecure Library
  make[1]: *** No rule to make target 'xsecure_sha.o', needed by 'libxilsecure.a'.  Stop.
  Makefile:27: recipe for target 'psu_cortexa53_0/libsrc/xilsecure_v1_0/src/make.libs' failed
  make: *** [psu_cortexa53_0/libsrc/xilsecure_v1_0/src/make.libs] Error 2

Fixing this by adding a pattern rules matching the required object files.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Bhavik Ameta <bameta@xilinx.com>
2015-07-31 16:56:17 +05:30
Soren Brinkmann
c8bca6ce1a xilsecure: Remove dead code
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Bhavik Ameta <bameta@xilinx.com>
2015-07-31 16:56:16 +05:30
Nava kishore Manne
cabafea458 Fix for standalone os tcl to support MultiBd and Packaged Bd
Acked-for-series: Naga Sureshkumar Relli <nagasure@xilinx.com>
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
2015-07-31 16:56:15 +05:30
Nava kishore Manne
a96825c608 Fix for xilikernel os tcl to support MultiBd and Packaged Bd
Acked-for-series: Naga Sureshkumar Relli <nagasure@xilinx.com>
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
2015-07-31 16:56:15 +05:30
Kinjal Pravinbhai Patel
73e7150785 sw_apps: openamp: modified rpc_demp application
This patch modifies openamp rpc_demo application to
remove the hardcoded shared memory region and support for the
memory region configuration as per requirement of the code
in MPU region settings

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi   <anirudh@xilinx.com>
2015-07-31 16:56:07 +05:30
Kinjal Pravinbhai Patel
31b60a0499 sw_apps: openamp: modified echo_test application
This patch modifies openamp echo_test application to
remove the hardcoded shared memory region and support for the
memory region configuration as per requirement of the code
in MPU region settings

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi   <anirudh@xilinx.com>
2015-07-31 16:56:05 +05:30
Kinjal Pravinbhai Patel
078a7131d6 sw_apps: openamp: modified matrix_multiply application
This patch modifies openamp matrix_multiply application to
remove the hardcoded shared memory region and support for the
memory region configuration as per requirement of the code
in MPU region settings

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi   <anirudh@xilinx.com>
2015-07-31 16:56:04 +05:30
Kedareswara rao Appana
60efc68c14 lib: bsp: Add UPPER_32_BITS and LOWER_32_BITS macro's
UPPER_32_BITS(x) macro to handle shifts that may be >= the width of
the data type.
LOWER_32_BITS(x) macro to handle masking of 32-bit data types.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Anirudha Sarangi   <anirudh@xilinx.com>
2015-07-31 16:55:53 +05:30
Kinjal Pravinbhai Patel
1f3de84cd2 bsp: a53: added memory attribute definition in xil_mmu.h
This patch adds various memory attribute definition
which can be used along with xil_settlbattributes API to
mark certain memory region with required attributes
such as cacheable or non-cacheable, inner/outer/non shareable
or executable or not etc.

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi   <anirudh@xilinx.com>
2015-07-31 16:55:51 +05:30
Kinjal Pravinbhai Patel
39f94f2135 bsp: a53: change in boot.s to include more memory attributes
This patch inclues memory attributes like device memory and
write through cacheable memory attributes to memory
attribute index register in boot.S

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi   <anirudh@xilinx.com>
2015-07-31 16:55:49 +05:30
Soren Brinkmann
59de0ec3be xilffs: Fix make rules
When building xilffs with '-rR' as arguments to make causes this error:
  Compiling XilFFs Library
  gmake[2]: *** No rule to make target 'ff.o', needed by 'libxilffs.a'.  Stop.
  Makefile:27: recipe for target 'psu_cortexa53_0/libsrc/xilffs_v3_1/src/make.libs' failed
  gmake[1]: *** [psu_cortexa53_0/libsrc/xilffs_v3_1/src/make.libs] Error 2

Fixing this by adding a pattern rules matching the required object files.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-07-31 16:55:48 +05:30
Mirela Simonovic
c064d50c14 PMUFW: PM: Added missing power up/down behavior for GpuPPs
-GpuPP now has its own PmSlave derived structure and the FSM
 (new structure is added because there is no peripheral with
 exactly the same behavior - Usbs have also their own power island,
 but compared to them GpuPPs do not have wake-up capabilities
 through GIC Proxy, and GpuPPs depend on FPD while LPD is
 considered always-on)

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Tested-by: Rohit Fule <rohitf@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
2015-07-31 16:55:46 +05:30
Mirela Simonovic
3283e01d23 PMUFW: xpfw_rom_interface.h: Added inline functions for power up/down GpuPPs
-Added missing power up/down inline functions for graphic processors
 needed by power management/GpuPP's FSM

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Tested-by: Rohit Fule <rohitf@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
2015-07-31 16:55:44 +05:30
Davorin Mista
860c409ea5 PMUFW: PM: Remove error-only acknowledge option
Signed-off-by: Davorin Mista <davorin.mista@aggios.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
2015-07-31 16:55:43 +05:30
Soren Brinkmann
1f36fb5736 PMUFW: ROM interface: Fix hook table type
The ROM handlers and hooks have a different signature.

Fixes: aea3444396c3 'ROM interface: Add ROM hook table'
Cc: Kristopher Bechamp <kristop@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
2015-07-31 16:55:41 +05:30
Filip Drazic
09090a4bc5 PMUFW: PM: slave: Added slave peripherals
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
2015-07-31 16:55:40 +05:30