Commit graph

987 commits

Author SHA1 Message Date
Nava kishore Manne
abc435be7c emaclite: Updated @addtogroup with appropriate version infromation.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
2015-08-08 11:10:37 +05:30
Nava kishore Manne
b52173e3e4 axipmon: Updated @addtogroup with appropriate version infromation.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
2015-08-08 11:10:30 +05:30
Nava kishore Manne
ff3a74d87a coresightps_dcc: Updated @addtogroup with appropriate version infromation.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
2015-08-08 11:10:22 +05:30
Nava kishore Manne
de9fff832f cpu_cortexr5: Updated @addtogroup with appropriate version infromation.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
2015-08-08 11:10:15 +05:30
Nava kishore Manne
71caca5066 iomodule: Updated @addtogroup with appropriate version infromation.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
2015-08-08 11:10:08 +05:30
Nava kishore Manne
d6ff63b394 uartlite: Updated @addtogroup with appropriate version infromation.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
2015-08-08 11:10:01 +05:30
Nava kishore Manne
dd7b7cb23f emacps: Updated @addtogroup with appropriate version infromation.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
2015-08-08 11:09:53 +05:30
Nava kishore Manne
16c2c7689e axivdma: Updated @addtogroup with appropriate version infromation.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
2015-08-08 11:09:37 +05:30
Nava kishore Manne
31a4c62837 axidma: Updated @addtogroup with appropriate version infromation.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
2015-08-08 11:09:25 +05:30
Nava kishore Manne
f49038f773 axicdma: Updated @addtogroup with appropriate version infromation.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
2015-08-08 11:08:50 +05:30
Jyotheeswar Reddy
b3ce29e2a1 PMUFW: Core: Clear DONT_SLEEP bit during initialization
DONT_SLEEP bit in PMU GLobal control register, if set,  wakes up the
microblaze from sleep state. This makes the "sleep" instruction
ineffective by making the MB to toggle between sleep and wake states
in the core loop. So this bit is cleared to prevent such a situation
and ensure that MB wakes up only in case of an interrupt event.

Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2015-08-07 18:39:03 +05:30
Jyotheeswar Reddy
4ae20ca9bf PMUFW: Headers: Remove unused register definitions from PMU Local
Some registers in PMU Local register set are not intended to be
published out. So removing all register definitions which are not
used by PMU FW currently.

Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
Tested-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2015-08-07 18:38:47 +05:30
Jyotheeswar Reddy
07377abe62 PMUFW: Exceptions: Log exception details and set FW error bit
Exception handler is modified to log the ESR and EAR registers
into persistent global storage registers(0,1) and set FW error bit-0.
If bit-0 of FWError group in ERROR_2 register set is configured to do
a SRST,then post reset, SW can read the reason for exception from
these persistent registers.

Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
2015-08-07 18:38:28 +05:30
Jyotheeswar Reddy
fd53261bc5 PMUFW: IPI: Add IPI Framework
Basic APIs are provided for modules to send/receive IPI messages.
These are wrappers around IPI driver functions and are intended to
support a common message structure. Currently only a module's IPI ID
is considered.This can be extended to include checksum and other fields in
IPI message and dispatching IPIs based on module id.

Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
2015-08-07 18:38:07 +05:30
Jyotheeswar Reddy
15dfa120ad PMUFW: EM: Integrate new Error Management framework as a module
This patch integrates the new EM framework and removes
redundant error handler files

Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
2015-08-07 18:37:40 +05:30
Jyotheeswar Reddy
a414510d6a PMUFW: EM: Add new error management framework
A framework to enable handling of HW errors reported via ERROR_1 and ERROR_2
registers in PMU GLOBAL space is provided. User can choose to register an
action for an error by using the provided API. An API is provided to enable
Error reporting via PSERR pin.

Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
2015-08-07 18:37:18 +05:30
Jyotheeswar Reddy
63266cf2b9 PMUFW: Scheduler: Fix interval comparision logic
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
2015-08-07 18:36:51 +05:30
Jyotheeswar Reddy
54d744d315 PMUFW: Core: Add API to remove a task from scheduler
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
2015-08-07 18:36:15 +05:30
Jyotheeswar Reddy
40cd4f3229 PMUFW: Mod: Add CSU lock down request to legacy module
Register for secure lock-down request from CSU and
call the corresponding ROM handler when this event occurs

Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
2015-08-07 18:35:33 +05:30
Jyotheeswar Reddy
7968c6a661 PMUFW: Interrupts: Add CSU secure lock down interrupt handler
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
2015-08-07 18:35:12 +05:30
Jyotheeswar Reddy
f5b94e4ea2 PMUFW: Events: Add CSU secure lock down request events
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
2015-08-07 18:34:27 +05:30
Jyotheeswar Reddy
b7d22226d9 PMUFW: Interrupts: Fix Event IDs in debug message
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
2015-08-07 18:33:57 +05:30
Jyotheeswar Reddy
6b0ba64eda PMUFW: MOD: Add new module for legacy power request handling
CSU ROM and FSBL send power up/down requests to PMU via the
PWR_UP/PWR_DN request register in PMU_GLOBAL. This module
handles these requests and routes them to respective ROM handlers

Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
2015-08-07 18:33:11 +05:30
Jyotheeswar Reddy
bc66b745b7 PMUFW: Events: Add REQ_PWRUP and REQ_PWRDN events
Add new events and supporting functions to handle legacy
ROM power up and power down requests that are initiated
using PMU GLOBAL registers.

Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
2015-08-07 18:32:51 +05:30
Jyotheeswar Reddy
6fe99fac43 PMUFW: MOD: Add DAP Wake Module
Add DAP event handler to PMU Firmware as a new user module and pass on
the handling to respective ROM Handlers.When a DAP wake arrives,
PMU should ACK the DAP Wake using its local registers.
PMU ROM has handlers for these and we will re-use these handlers here.
This module is enabled only if ENABLE_PM is not defined to avoid conflict
with the PM module

Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
2015-08-07 18:23:31 +05:30
Suneel Garapati
9a13c33ea1 lib: sw_apps: freertos support for latest bsp
change to freertos821_xilinx version

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Acked-by: Anirudha Sarangi   <anirudh@xilinx.com>
2015-08-07 16:10:39 +05:30
Nava kishore Manne
69f6f49627 Move @details before driver description
Move @details before driver description

Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Reviewed-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
2015-08-07 16:07:18 +05:30
Rohit Fule
6c9a54d19b PMUFW: PM: Modified serial ordering of PM API ids
This patch removes the gap in serial numbering of PM API ids
between PM_SET_MAX_LATENCY and PM_RESET_ASSERT defined in
pm_defs.h

Signed-off-by: Rohit Fule <rohitf@xilinx.com>
Tested-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
2015-08-07 16:03:33 +05:30
Rohit Fule
652be149c6 sw_services:xilpm: Modified serial ordering of PM_API ids
This patch removes clock related PM API ids defined in pm_defs.h
under sw_services and reassigns ids in serial order.

Signed-off-by: Rohit Fule <rohitf@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
2015-08-07 16:01:41 +05:30
Sarat Chand Savitala
61bd977834 sw_apps:zynqmp_fsbl: Corrected the logic used to determinte A53 Execution state
Execution state of A53 (64-bit/32-bit) is now determined based on __aarch64__ value

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
2015-08-07 16:01:05 +05:30
Nava kishore Manne
88a48effad Retain @details only in the primary header file. Removed all other instances
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Reviewed-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
2015-08-07 16:00:18 +05:30
Naga Sureshkumar Relli
2b86552aef iomodule: Fix Iomodule UART receive interrupt detection.
This patch updates the XIOModule_Uart_InterruptHandler to
read ISR Register instead of reading Interrupt pending register.

Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Reviewed-by: Kedareswara rao Appana <appanad@xilinx.com>
2015-08-07 15:59:23 +05:30
Sarat Chand Savitala
84204047c7 sw_apps:zynqmp_fsbl: Added A53 32-bit support in FSBL
This patch adds support for FSBL running in A53 32-bit mode and
also supports handing off to A53 32-bit applications from FSBL.

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
2015-08-06 15:33:14 +05:30
Andrei-Liviu Simion
754a82e98b dp: rx: Enable enhanced framing mode and training pattern 3 if DP v1.2.
As per specification.
- Always enable enhanced framing mode.
- Declare training pattern 3 support if core is DP v1.2.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
2015-08-05 21:15:24 +05:30
Andrei-Liviu Simion
d972cf8c18 dp: tx: Added link configuration and training callbacks.
New callbacks for:
- Link rate changes.
- Lane count changes.
- Pre-emphasis and voltage swing adjust request.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
2015-08-05 21:15:08 +05:30
Andrei-Liviu Simion
941a63a7b9 dp: Updated comments.
Added missing revision history comments.
Added missing Doxygen @addtofile closing parenthesis.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
2015-08-05 21:14:53 +05:30
Andrei-Liviu Simion
0e5f54a853 dp: Guard interrupts against uninitialized callbacks.
If an interrupt occurs without a user defined callback, don't invoke the
function.
Otherwise, unexpected behavior will be seen due to running code from 0x0 (NULL).

Prior to this, it was the responsibility of the user to ensure all callbacks for
interrupts were set.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
2015-08-05 21:14:36 +05:30
Andrei-Liviu Simion
83cfd59989 dp: rx: Fix interrupt masking.
The interrupt mask and interrupt cause registers are independent. The interrupt
handler has been modified to ignore interrupts that have been masked out.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
2015-08-05 21:14:24 +05:30
Andrei-Liviu Simion
0ebb5dbdfe dp: HDCP additions and unplug interrupt.
Added new interrupts, callbacks, and macros related to HDCP (High-bandwidth
Digital Content Protection).
Added new interrupts, callbacks, and macros for an unplug event.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
2015-08-05 21:13:44 +05:30
Andrei-Liviu Simion
f3e3c76a68 dp: Cleaned up CfgInitialize.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
2015-08-05 21:13:21 +05:30
Andrei-Liviu Simion
761ae699f7 dp: Fixed compilation warnings.
Fixed compilation warnings when using:
-Wall -Wextra

No need for ">=0" assertions on arguments that are of unsigned type.
Removed unused variables.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
2015-08-05 21:13:05 +05:30
Andrei-Liviu Simion
dd5ecd1b10 dp: tx: Fractional byte calculation is scaled by 1024 instead of 1000.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
2015-08-05 21:12:46 +05:30
Andrei-Liviu Simion
0f275f26d7 dp: rx: Renamed interrupt + timer example to reflect SST + DP159.
The naming of this example is better described as SST with DP159
functionality.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
2015-08-05 21:12:20 +05:30
Andrei-Liviu Simion
bd2d7b4487 dp: rx: Added DP159 programming sequence to example.
The programming sequence required by the DP159 retimer has been
added.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
2015-08-05 21:11:57 +05:30
Andrei-Liviu Simion
fc4dca3846 dp: rx: Updated timer usage in examples.
Set the reset value for the timer upon initialization.
Use the timer ID as an argument for consistency with the other
device IDs.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
2015-08-05 21:11:28 +05:30
Andrei-Liviu Simion
29952963ce dp: rx: Add DP159 dependencies to initialization.
Using the DP159 solution, 8 ms needs to be used as the AUX training
interval.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
2015-08-05 21:10:05 +05:30
Andrei-Liviu Simion
513926d80a dp: rx: Added macros for the training settings and CDR control.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
2015-08-05 21:09:12 +05:30
Andrei-Liviu Simion
8518d9a3da dp: rx: Optimized initialization.
RX initialization is not dependent on PLL and reset checks.
- Training will not be initiated until the RX is ready.

The clock is transmitted only once the cable is connected.
- This means that the CPLLs will never lock if no cable is plugged
in resulting in DP RX core initialization time out.

Moved core and interrupt mask enables towards end of function.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
2015-08-05 21:08:46 +05:30
Andrei-Liviu Simion
3b39183e40 video_common: Updated version to v2.0.
Due to DP159 API additions.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
2015-08-05 21:06:08 +05:30
VNSL Durga
7ca1fb1844 xilskey: Modified example and input.h files
Example has been modified to support both Zynq PL eFuse and
Ultrascale eFuse. Added GPIO pins and channels to access
Master Jtag through GPIO and RSA key hash, AES's CRC value
input macros are also added.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-08-05 21:05:52 +05:30