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Author SHA1 Message Date
Sarat Chand Savitala
c7791d8bb0 sw_services:xilsecure: Secure bitstream support added 
This patch adds support to decrypt PL bitstream.

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
 2015-06-22 11:31:52 +05:30
Sarat Chand Savitala
3b07202f16 sw_apps:zynqmp_fsbl: Added PL bitstream support 
PL bitstream download support added.
Both secure and non-secure bitstreams are supported.

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
 2015-06-20 13:08:13 +05:30
Sarat Chand Savitala
a01d2a94ac sw_services:xilsecure: Fix to avoid clearing of AES key 
Clearing the CSU_AES_KEY_CLEAR register to avoid clearing of AES key.

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
 2015-06-19 17:57:08 +05:30
Venkata Naga Sai Krishna Kolapalli
b07d492a65 Standalone BSP : Add Coresight DCC support in .mld 
This patch adds coresight DCC support for Zynq Ultrascale+
MP Platform by modifying stdin and stdout range options.

Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
 2015-06-17 15:13:24 +05:30
Kinjal Pravinbhai Patel
3459d888f6 bsp: r5: removes Init_Uart call from boot flow 
This patch modifies xil-crt0.S to remove Init_Uart API call
as fsbl is initializing the UART

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
 2015-06-17 14:50:51 +05:30
Kinjal Pravinbhai Patel
46c5e55478 bsp: a53: removes Init_Uart call from boot flow 
This patch modifies xil-crt0.S to remove Init_Uart API call
as fsbl is initializing the UART

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
 2015-06-17 14:50:51 +05:30
Kinjal Pravinbhai Patel
d0c41612d8 bsp: r5: enabling the asynchronous abort in boot code 
This patch unmasks the A bit in CPSR to enable the
asynchronous abort in boot.S

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
 2015-06-17 14:50:50 +05:30
Kinjal Pravinbhai Patel
3f2478472f bsp: a53: enabling the SError exception in boot code 
This patch enables Serror exception in boot flow for catching the
asynchronous aborts

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
 2015-06-17 14:50:50 +05:30
Kinjal Pravinbhai Patel
99a46157eb bsp: a53: added support for 64bit addressing mode 
This patch modifies Xil_DCacheFlushRange, Xil_DCacheInvalidateRange
and Xil_ICacheInvalidateRange API to add support for addresses higher
than 4GB by not truncating the addresses to 32bit

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
 2015-06-17 14:50:50 +05:30
Soren Brinkmann
c4df8f0dd2 PMUFW: lscript: Add section for ROM extension table 
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
 2015-06-17 14:24:09 +05:30
Soren Brinkmann
d185a3a6d1 PMUFW: lscript: Sync memory definition with PMUFW repo 
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
 2015-06-17 14:24:08 +05:30
Soren Brinkmann
368c173e5d PMUFW: lscript: Remove redundant blank lines 
Sync with PMUFW sources.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
 2015-06-17 14:24:08 +05:30
Sarat Chand Savitala
fd800dfb46 sw_apps:zynqmp_fsbl: Removed redundant calls to Xil_DCacheFlush() 
Xil_DCacheDisable() function internally has call to Xil_DCacheFlush().
Hence removing redundant calls to Xil_DCacheFlush from FSBL.

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
 2015-06-10 20:36:58 +05:30
Sarat Chand Savitala
4766bcb9f6 sw_apps:zynqmp_fsbl: Registering exception handlers 
Exception handlers are now registered unconditionally for both A53 and R5
Removed enabling of IRQ from FSBL(to be enabled in user application)

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
 2015-06-10 20:36:57 +05:30
Sarat Chand Savitala
83eaa550d6 sw_apps:zynqmp_fsbl: Updated release version to 2015.3 
Updated release version from 2015.1 SW Beta2 to 2015.3

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
 2015-06-10 20:36:56 +05:30
naga sureshkumar relli
d9923bc7bf xilflash_v4_1: Fix Write buffer programming for IntelStrataFlash 
This patch fixes the writebufer programming for IntelStrataFlash.

Signed-off-by: naga sureshkumar relli <nagasure@xilinx.com>
 2015-06-10 20:36:54 +05:30
naga sureshkumar relli
3b8769e4f8 xilflash_v4_1: Fix warnings. 
This patch fixes the warnings.

Signed-off-by: naga sureshkumar relli <nagasure@xilinx.com>
 2015-06-10 20:36:52 +05:30
naga sureshkumar relli
cc85685a73 xilflash_v4_1: Fix Spansion write buffer programming. 
This patch fixes the spansion write buffer programming
issue.

Signed-off-by: naga sureshkumar relli <nagasure@xilinx.com>
 2015-06-10 20:36:51 +05:30
naga sureshkumar relli
6c21998270 xilflash_v4_0: deprecated version 4.0 and created new version 4.1 
This patch deprecates the xilflash_v4_0 and
creates new version xilflash_v4_1.

Signed-off-by: naga sureshkumar relli <nagasure@xilinx.com>
 2015-06-10 20:36:49 +05:30
Kinjal Pravinbhai Patel
7307299d94 bsp: a9: modified translation_table.s for DDR-less system 
This patch modifies translation_table.S to put check whether
the DDR is present or not to fix the compilation error in
case of DDR-less system

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
 2015-06-10 20:18:18 +05:30
Kinjal Pravinbhai Patel
4baf4b5e6e bsp: a53: added src files for cortex-a53 32bit mode 
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
 2015-06-08 12:07:35 +05:30
Kinjal Pravinbhai Patel
6b6e985817 bsp: r5: removed xmpu, slcr, xppu header files from cortexr5 folder 
This patch removes xmpu, slcr, xppu header files from cortexr5 folder
and standalone tcl has been modified to copy the header files from
cortexa53/includes_ps. Makefile has been modified to include the
header files in include folder while compilation

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
 2015-06-08 12:07:33 +05:30
Kinjal Pravinbhai Patel
9b5cb9a6de bsp: a53: rearranging the Cortex A53 folder structure 
This patch creates folder 64bit to accomodate cortex-a53 64bit
mode BSP files and creates another folder includes_ps for
xmpu, xppu, slcr header files. It also changes the standalone tcl to
reflect the necessary changes

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
 2015-06-08 12:07:32 +05:30
Kinjal Pravinbhai Patel
b2f279c410 bsp: a53: added interrupt IDs for RTC 
This patch modifies xparameters_ps.h to include RTC interrupt IDs

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
 2015-06-08 12:07:30 +05:30
Kinjal Pravinbhai Patel
f6ab7e5199 bsp: r5: added interrupt IDs for RTC 
This patch modifies xparameters_ps.h to include RTC interrupt IDs

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
 2015-06-08 12:07:30 +05:30
Kinjal Pravinbhai Patel
54eda83e22 bsp: deprecated the older version 5.1 and created new minor vesion 5.2 
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<head>
<meta http-equiv="Content-Type" content="text/html; charset=us-ascii">
<meta name="Generator" content="Microsoft Word 15 (filtered medium)">
<style><!--
/* Font Definitions */
@font-face
	{font-family:"Cambria Math";
	panose-1:2 4 5 3 5 4 6 3 2 4;}
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	{mso-style-type:personal-compose;
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	{mso-style-type:export-only;
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	{size:8.5in 11.0in;
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<o:shapedefaults v:ext="edit" spidmax="1026" />
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<div class="WordSection1">
<p class="MsoNormal">Hi,<o:p></o:p></p>
<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
<p class="MsoNormal">I have attached standalone BSP patch for deprecating the older version and creating a new version as it is a big patch<o:p></o:p></p>
<p class="MsoNormal">It is located at <o:p></o:p></p>
<p class="MsoNormal">/proj/epdsw2/kinjal/2015.2/0001-bsp-deprecated-the-older-version-5.1-and-created-new<o:p></o:p></p>
<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
<p class="MsoNormal">Regards,<o:p></o:p></p>
<p class="MsoNormal">Kinjal<o:p></o:p></p>
<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
</div>
</body>
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From 256718ca92a9b3407cac916c7c5c3ab048488aaa Mon Sep 17 00:00:00 2001
From: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Date: Thu, 28 May 2015 17:10:25 +0530
Subject: [EMBEDDEDSW PATCH 1/6] bsp: deprecated the older version 5.1 and created new minor vesion 5.2

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
 2015-06-08 12:07:28 +05:30
P L Sai Krishna
01c429ca1a xilisf: Modified the check in flash read APIs for parallel case. 
This patch modifies the check for whether bank crossover
in flash read functions for parallel case. This will fix
the bug where wrap around occurs to the top of flash when
reading very bottom..

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
 2015-06-04 13:09:43 +05:30
P L Sai Krishna
dbff6b1fe4 xilisf: Created new minor version. 
This patch deprecates the xilisf_v5_2 and created new
minor version xilisf_v5_3.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
 2015-06-04 13:09:42 +05:30
Soren Brinkmann
159e188d9d xilpm: Remove useless assignments from enum declarations 
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
 2015-06-03 18:40:00 +05:30
Soren Brinkmann
69bae79a14 xilpm: Expand 'req' to 'request' 
To avoid confustion between request vs requirement, spell them out.

Scripted change:
  find -type f -name "*.[chS]" -exec sed -i -e 's/PM_REQ_WAKEUP/PM_REQUEST_WAKEUP/g' -e 's/PM_REQ_SUSPEND/PM_REQUEST_SUSPEND/g' -e 's/PM_REQ_NODE/PM_REQUEST_NODE/g' -e 's/REQ_ACK_NO/REQUEST_ACK_NO/g' -e 's/REQ_ACK_BLOCKING/REQUEST_ACK_BLOCKING/g' -e 's/REQ_ACK_CB_STANDARD/REQUEST_ACK_CB_STANDARD/g' -e 's/REQ_ACK_CB_ERROR/REQUEST_ACK_CB_CERROR/g' -e 's/IPI_BUFFER_REQ_OFFSET/IPI_BUFFER_REQUEST_OFFSET/g' -e 's/XPm_ReqSuspend/XPm_RequestSuspend/g' -e 's/XPm_ReqWakeUp/XPm_RequestWakeUp/g' -e 's/XPm_ReqNode/XPm_RequestNode/g' '{}' ';'

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
 2015-06-03 18:40:00 +05:30
Sarat Chand Savitala
97bbdf3d03 sw_apps:zynq_fsbl: Updated release version to 2015.2 
Updated release version from 2015.1 to 2015.2

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
 2015-05-22 12:20:02 +05:30
Nava kishore Manne
1726f14574 lib:sw_apps:standalone drivers license changes 
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
 2015-05-16 14:37:24 +05:30
Nava kishore Manne
1624cbc10e lib:bsp:standalone drivers license changes 
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
 2015-05-16 11:52:35 +05:30
Nava kishore Manne
398cbdc152 lib:sw_services:standalone drivers license changes 
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
 2015-05-15 14:48:25 +05:30
Harini Katakam
19801ef984 xilffs: Card check only if card detect signal is present 
Check for card detection only if that signal is present
(based on HAS_CD macro)

Signed-off-by: Srinivas Goud <srinivas.goud@xilinx.com>
Signed-off-by: Harini Katakam <harinik@xilinx.com>
 2015-05-14 22:23:54 +05:30
Harini Katakam
2e8bfd71a8 xilffs: Add card check logic to support Zynq Ultrascale+ MPSoC 
Add card detection logic as per Zynq Ultrascale+ MPSoc specification.

Signed-off-by: Srinivas Goud <srinivas.goud@xilinx.com>
Signed-off-by: Harini Katakam <harinik@xilinx.com>
 2015-05-14 22:23:54 +05:30
P L Sai Krishna
ca1fb25835 xilffs_v3_1: Added new minor version. 
This patch add new minor version v3.1 and deprecates v3.0

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
 2015-05-14 22:23:54 +05:30
Sarat Chand Savitala
2374e5de1c sw_apps:zynqmp_fsbl: xilsecure library selection by default 
While creating new FSBL+BSP project, made xilsecure library
to be selected by default. This avoids compilation errors
when FSBL project is created.

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
 2015-05-14 07:55:03 +05:30
Soren Brinkmann
9383db5c21 xilsecure: Don't consider directory components in toolchain check 
The makefile tries to detect gnu vs ARM toolchain by string-comparing
the COMPILER with some hardcoded values. This fails when the toolchain
is specified with directory components. Hence, remove directory
components from the tests.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
 2015-05-13 11:06:43 +05:30
Bhavik Ameta
ec8a0b20f7 sw_services:xilsecure_v1_0: resolved AES and RSA failures 
DMA interrupt clearing after each transfer in AES
resolved RSA failure due to incorrect data type

Signed-off-by: Bhavik Ameta <bameta@xilinx.com>
 2015-05-05 23:42:49 +05:30
Sarat Chand Savitala
d7d271eb97 sw_apps:zynqmp_fsbl: Fix to make decryption work when authentication disabled 
When authentication of partitions is not enabled, decryption is failing.
This patch fixes this issue.

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
 2015-05-05 23:29:41 +05:30
Sarat Chand Savitala
380e426371 sw_apps:zynqmp_fsbl: Changes in FSBL as per the current xilsecure library 
This patch does the changes in FSBL to match the signature changes of
few functions in xilsecure library.

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
 2015-04-27 17:37:44 +05:30
Soren Brinkmann
4b7afd3d4e xilpm: Remove stdint.h 
Migrate to the standard standalone types.

Scripted change:
  find -type f -name "*.[ch]" -exec sed -i -e 's/uint32_t/u32/g' -e 's/uint8_t/u8/g' -e 's/uint16_t/u16/g' '{}' ';'
  find -type f -name "*.[ch]" -exec sed -i -e 's/int32_t/s32/g' -e 's/int8_t/s8/g' -e 's/int16_t/s16/g' '{}' ';'

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
 2015-04-24 11:57:12 +05:30
Soren Brinkmann
1a875cb79f xilpm: Remove pm_this_cpuid 
Remove this unused macro.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
 2015-04-24 11:57:11 +05:30
Soren Brinkmann
a8b9765edc xilpm: Move common parts to common header 
The pm_client.h headers hold processor specific information. Move common
information to the common header.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
 2015-04-24 11:57:11 +05:30
Soren Brinkmann
92747ad56a xilpm example: Remove GicEnableInterrupt() 
The function is just a trivial wrapper => inline.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
 2015-04-24 11:57:11 +05:30
Soren Brinkmann
fcd1ad8d4e xilpm example: Remove gic_setup_handler() 
The function is just a trivial wrapper and used once only. Just inline
it.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
 2015-04-24 11:57:10 +05:30
Soren Brinkmann
bb2e0bdb77 xilpm: Clean up 
Fix some white space and comment issues.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
 2015-04-24 11:57:10 +05:30
Jyotheeswar Reddy
4350a1fa00 sw_apps:zynqmp_pmufw: Clear IPI0 status register during core init 
swbeta2 commit 1b173007d1cc009bffeb2969a5a5bacc533647db

IPI0 is used by PMUFW for PM requests and the mask is used for determining
 the Master. There are chances of IPIs being triggered before FW Init but
un-handled or even bits that are not cleared by ROM, causing a corruption
of the ISR mask. So PMUFW should cleanup these bits during startup

Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
 2015-04-24 11:57:10 +05:30
Soren Brinkmann
12c2e29937 PMUFW: Release RPU island reset on power up 
swbeta2 commit 572db0eb0f48b4f7f5684abea721c6fac92ccdee

When powering up the RPU island the individual RPU core resets as well
as the reset for the whole island are asserted. To ensure proper resume,
the island reset needs to be released when the island is powered up.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
 2015-04-24 11:57:09 +05:30