b7e5bfead2
harmonize codestyle
2020-06-11 18:38:46 +02:00
77b55f65f7
use new plugin mechanism
2020-06-11 18:19:03 +02:00
d5b1012b75
intc: fix name of register space
2020-06-11 15:57:05 +02:00
6882e9d418
harmonize code-style with VILLAScommon/node
2020-06-11 14:26:38 +02:00
c906116d86
update to latest VILLAScommon submodule
2020-06-11 14:20:33 +02:00
3b28eea7d2
aurora_axis: add two functions to reset counters and configure loopback mode
2020-06-11 13:08:42 +02:00
3d15323376
aurora_axis: harmonize with HDL changes
2020-06-11 13:01:27 +02:00
Hatim Kanchwala
4005a0b40e
Merge branch 'master' of git.rwth-aachen.de:acs/public/villas/VILLASfpga
2020-06-02 00:54:54 +02:00
Hatim Kanchwala
bf67a2e5f0
Add initial Aurora driver
2020-06-02 00:54:31 +02:00
02f60eb86e
add a writeMemory function to IpCore class
2020-05-26 15:24:15 +02:00
Hatim Kanchwala
73e85f2e5a
Add intial header file for Aurora
2020-05-26 14:46:35 +02:00
f6a78bea69
dma: add dump() method
2019-08-15 13:54:58 +02:00
Hatim Kanchwala
bf74db8e79
Debug update
2019-06-24 12:11:44 -04:00
2112038d70
Merge branch 'feature/hls-rtds2gpu' into develop
2018-08-21 13:51:32 +02:00
76b1695586
move more code to VILLAScommon repo
2018-08-21 13:27:04 +02:00
df89b63368
fix include paths
2018-08-21 11:07:53 +02:00
Daniel Krebs
b2698c8bd5
rtds2gpu: update register type to work for more complex payloads
2018-07-26 16:49:06 +02:00
Daniel Krebs
0cdc05c3d5
rtds2gpu: add struct for memory layout of rtds2gpu buffer
2018-07-11 16:06:48 +02:00
7409d2024d
add more copyright / license headers
2018-06-25 17:03:09 +02:00
7fd6599ea6
update copyright years
2018-06-25 15:33:14 +02:00
Daniel Krebs
d853d5e0d3
wip GPU RTT
2018-06-06 09:55:14 +02:00
Daniel Krebs
49f0c2e0c4
unit test RTT via CPU to/from RTDS works!
2018-06-04 19:06:36 +02:00
Daniel Krebs
92bfe849b4
ips/rtds2gpu: use new connect interface
2018-06-04 17:36:36 +02:00
Daniel Krebs
f413712b86
gpu2rtds: unit test working
2018-06-04 17:36:36 +02:00
Daniel Krebs
010e0c3681
hls: add base HLS IP and enable virtual multi-inheritance
...
Virtual inheritance is required because (for example) the Rtds2Gpu
IP inherits from Hls and IpNode who both inherit from IpCore.
2018-06-04 17:36:36 +02:00
Daniel Krebs
5c67dc3727
rtds2gpu: update vlnv to match v1.1 and adapt config to new bitstream
2018-06-04 17:36:15 +02:00
Daniel Krebs
28458fdf8a
update rtds2gpu HLS IP to v1.1
...
- better tested IP (testbenches)
- detect invalid frame sizes
- more status reporting
2018-06-04 17:36:15 +02:00
Daniel Krebs
bf286568dd
rtds2gpu IP works
2018-06-04 17:36:15 +02:00
Daniel Krebs
47bd186f5e
ip-node: move stream graph to IpNode and add easy-to-use connect interface
2018-06-04 17:31:12 +02:00
Daniel Krebs
28143e7188
ips/rtds: add C++ version of RTDS IP
2018-06-04 14:20:06 +02:00
Daniel Krebs
a93278b74e
ips/dma: expose names of its treaming ports
2018-06-04 14:20:06 +02:00
Daniel Krebs
8e63785073
ips/dma: change interface, get byte count from {read,write}Complete()
2018-06-04 14:20:06 +02:00
Daniel Krebs
7479675361
ips/intc: remove unused code
2018-06-04 14:20:06 +02:00
Daniel Krebs
2e339b406d
lib/ips: add data fifo IP needed for stream routing
2018-06-04 14:20:06 +02:00
Daniel Krebs
a0c5acce4c
ip-node: implement connect interface and update AxiStreamSwitch implementation
2018-06-04 14:20:06 +02:00
Daniel Krebs
a1daf95202
lib/card: lookup IP by identifier
2018-06-04 14:20:06 +02:00
Daniel Krebs
967e39e36c
ip-node: add implementation of StreamGraph for automatic routing
2018-06-04 14:20:06 +02:00
Daniel Krebs
5097827757
fix include paths, use <villas/...> style
2018-06-04 13:24:57 +02:00
Daniel Krebs
7dcdfaccd9
ips/dma: let user deal with making memory accessible to DMA
...
It is probably too costly to do (and verify) it on every read
or write. Furthermore, the user knows better how to make a certain
memory available to the DMA.
2018-05-15 18:04:24 +02:00
Daniel Krebs
89b5169a6e
ips/pcie: parse AXI/PCI BARs and create mappings to/from PCIe address space
...
This is used for translations that don't use VFIO which used to bridge
the PCIe address space by creating direct mappings from process VA to
the FPGA. When we want to communicate directly via PCIe without the
involvment of the CPU/VFIO, we need the proper translations that are
configured in the FPGA hardware.
2018-05-15 18:04:24 +02:00
Daniel Krebs
364b137156
fpga/card: make pci device a class member (needed later)
2018-05-15 18:04:24 +02:00
Daniel Krebs
8f3833bc73
ips/dma: rename pingpong to memcpy and always connect loopback
2018-05-15 18:04:24 +02:00
Daniel Krebs
3e505c74bf
ips/bram: add block RAM IP and use it with DMA test
2018-04-13 15:35:41 +02:00
Daniel Krebs
ae2bd2a41d
lib/ip: alias type for memory block name and cache addres space IDs in IP
2018-04-13 15:35:41 +02:00
Daniel Krebs
507ea77ad6
ips/dma: add (simple) DMA driver
2018-03-26 16:17:26 +02:00
Daniel Krebs
4f6694420f
lib: remove old and unused C files
2018-03-26 16:17:26 +02:00
Daniel Krebs
60882f1086
lib/memory: implement memory handling with allocators and blocks
...
This commit is 2/2 of a series of patches and not working on its own.
2018-03-26 16:17:20 +02:00
Daniel Krebs
b01a50184c
kernel/vfio: port to C++
...
This commit is 1/2 of a series of patches and not working on its own.
2018-03-26 16:16:42 +02:00
Daniel Krebs
676fd9171c
lib/ip: make logger a class member of IpCore
...
Logging is used everywhere and there's no justification of the clutter
and runtime overhead of `aut logger = getLogger();` everywhere.
2018-02-14 16:04:33 +01:00
Daniel Krebs
aa2b0b324f
lib/ips/pcie: use cached address space id and supply interface to create mapping
2018-02-14 14:34:03 +01:00
