This patch modifies .mld and .tcl files to provide the
Read_Only option to the user. By default this option
is false.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch removes compilation errors in xilffs library.
This errors are coming when we configure ReadOnly, use
StringFunctions and use LFN options. This patch also does
configuring _FS_READONLY macro based on the option given
by the user.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
if one xconstant is used for multiple lines then there are multiple entries
created. Prevent the same.
Signed-off-by: Kalyani Tummala <kalyani@xilinx.com>
Signed-off-by: Shubhrajyoti Datta <shubhraj@xilinx.com>
For SD and eMMC, BIN filenames now follow convention BOOTXXXX.BIN.
FSBL now updated as per this change.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
This patch removes compilation errors by enabling the
IntelStmFlashInitialize function for STM flash family
on DC1.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch modifies xil_mpu.c to add the API Xil_SetMPURegion
which provide the settings for a MPU region with size
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Specify the format attribute for the xil_printf() function to allow the
compiler to do printf-style checking of the format string and arguments.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Treat 'p' conversions as alias of 'x'. Strictly, not fully correct, but
better than ignoring them.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Treat 'X' conversions as alias of 'x'. Strictly, that is not fully
correct, but still better than ignoring them.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
This patch modifies testapp tcl to support peripheral test for
ZynqMP SOC by checking for a processor name
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch does following things:
---> Add support the hier IP (user parameters that got exported to xml/hdf file)
---> Remove redundant code for checking the type of target periphral
that got connected to axi ethernet provided an api for the same (axieth_target_periph).
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
The axiethernet ip contains 3 inbuilt blocks init
--> Axi Ethernet MAC
--> Axi Etherent BUF
--> PCS/PMA Core
During the vivado version < 2015.2 the axiethernet ip
being exported to hdf in flat mode and the hsi opens this in flat mode.
But from 2015.3 build onwards the axiethernet ip is tagged as core in the vivado
and hsi will open the ip in hier IP mode(hierarchy) means for user only
top level axiethernet instance will be visible and it will contains all
the properties related to the sub-cores.
In order to allow backward compatabilty
---> If a xml/hdf file which got created with the vivado version < 2015.3 being exported to
the sdk >= 2015.3.
---> Two drivers will be active to resolve this issue.
---> axiethernet_v4_4 will be attached to BUF this will fix the backward compatabilty issue.
---> axiethernet_v5_0 will be attached to top level block for newer features.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
This patch removes NULL pointer checks for Rx/Tx
buffers since writing/reading from 0x0 is permitted.
Used Tx/Rx flags to check for Writing/reading.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
The current timeout value is not enough for erase operation on slower
devices. so increasing the timeout value and also added usleep for
timeout routine to have a precise timeout.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
This patch add support for Macronix 512Mb flash and
corrected the if condition logic, by replacing equal-to
operator with equality operator.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch adds coresight DCC support for Zynq Ultrascale+
MP Platform by modifying stdin and stdout range options.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This patch modifies the if condition logic for ReadId
function in examples by replacing equal-to operator
with equality.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch modifies the Bus width value during dummy phase
in examples since it is recommended to be same as in
data phase.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch modifies xil-crt0.S to remove Init_Uart API call
as fsbl is initializing the UART
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies xil-crt0.S to remove Init_Uart API call
as fsbl is initializing the UART
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies Xil_DCacheFlushRange, Xil_DCacheInvalidateRange
and Xil_ICacheInvalidateRange API to add support for addresses higher
than 4GB by not truncating the addresses to 32bit
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Xil_DCacheDisable() function internally has call to Xil_DCacheFlush().
Hence removing redundant calls to Xil_DCacheFlush from FSBL.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Exception handlers are now registered unconditionally for both A53 and R5
Removed enabling of IRQ from FSBL(to be enabled in user application)
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
