This patch corrects the logic used to trigger PMU_0 IPI.
Also added code to Enable PMU_0 IPI.
Signed-off-by: RamyaSree <rdarapun@xilinx.com>
Acked-by: Sarat Chand Savitala <saratcha@xilinx.com>
This patch adds support for SD1 and SD1 with level shifter bootmodes in FSBL
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
UART initialization is now done correctly in psu_init file for emulation platforms.
Hence removing the workaround. Also, this workaround should not be present for
Silicon.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
Currently power state of island is checked before giving corresponding power up
request. This fix removes this check as this condition is false at reset and
leading to the corresponding power up request not being sent.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
tcl procedures are added to facilitate validating the FSBL supported processor(s)
and os platform.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
Currently R5 applications are handedoff immediately after they are loaded.
This feature is configurable in FSBL and now with this change, early handoff
is disabled by default. User can enable this feature again by defining
FSBL_EARLY_HANDOFF_EXCLUDE_VAL as 1.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
Except banner all prints are disabled in FSBL.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
When load address is not mentioned for PL bitstream, bootgen now makes this
as 0xFFFFFFFF to indicate it is invalid. Hence, FSBL uses default address to
load bitstream when load address from bootgen is 0xFFFFFFFF.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
Currently for R5, compiler flag for, floating-point ABI is mentioned
as "softfp". This causes abort on encountering floating point arithmetic
operation. Hence changing this flag to "soft".
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
This fix enables the compiler flags specified in HSI command line
to be appended to those specified in FSBL tcl file.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
Execution state of A53 (64-bit/32-bit) is now determined based on __aarch64__ value
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
This patch adds support for FSBL running in A53 32-bit mode and
also supports handing off to A53 32-bit applications from FSBL.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
As in JTAG bootmode, watchdog is not initialized, avoided stopping of
watchdog in JTAG bootmode.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
This patch modifies the buswidth in dummy phase as
in data phase.
Signed-off-by: RamyaSree <rdarapun@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This patch added Tx/Rx flags in qspi message format
according to qspipsu driver changes.
Signed-off-by: RamyaSree <rdarapun@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
PMU FW if present, is now handed off immediately after its load and validation.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
Support added to handoff to R5 applications after thery are loaded.
This feature can be turned ON by using conditional switch.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
Changed the location of temporary ddr address definition.
This address is for storing PL bitstream temporarily.
User can change this address till support is provided in bootgen
(for load address configuration for PL).
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
Added checks to power up power islands, if required, before first access.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
This fix stores FSBL's ATF Handoff parameters at fixed address towards
end of OCM so that ATF can avoid conflict with its sections.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
For SD and eMMC, BIN filenames now follow convention BOOTXXXX.BIN.
FSBL now updated as per this change.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Xil_DCacheDisable() function internally has call to Xil_DCacheFlush().
Hence removing redundant calls to Xil_DCacheFlush from FSBL.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Exception handlers are now registered unconditionally for both A53 and R5
Removed enabling of IRQ from FSBL(to be enabled in user application)
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
While creating new FSBL+BSP project, made xilsecure library
to be selected by default. This avoids compilation errors
when FSBL project is created.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
When authentication of partitions is not enabled, decryption is failing.
This patch fixes this issue.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
This patch does the changes in FSBL to match the signature changes of
few functions in xilsecure library.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Support for decryption of images added.
Authentication and decryption now use secure library APIs.
csu dma driver APIs are used now.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
These changes were present in master-sdk-beta2 and also need to be
applied to master as well.
Changes done are:
- Macro name change in QSPI for PSU naming change
- Workaround for QEMU in QSPI32 dummy mode
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
This patch adds call to check the supported OS platform when
application is Zynq MP FSBL.
This enables correct error message to be displayed when trying
to create FSBL project with OS platform other than Standalone.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Removing compiler optimization level and debug level flags from FSBL tcl file.
These flags can be passed on as arguments while compiling using make.
O2 optimization will be required while building FSBL to reduce the
size of FSBL and hence to accomodate ATF in OCM.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
