This patch does following things:
Added polling for transfer complete for cmd6 in case
of eMMC and MMC card.
Added 2.0 controller version check in case of eMMC to
switch for High speed mode in Zynq.
Added check for eMMC card, since HS200 mode switching
will only support by eMMC.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Acked-by: Harini Katakam <harinik@xilinx.com>
QEMU doesn't model PMU in signle arch. Since, in FSBL,
it couldn't be determined if QEMU is of single or
multi arch, for now skipping power-up request for both cases.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
This reverts commit 73154541df.
Linker script was modified to work-around a bootgen issue with handling
multiple loadable sections. Now this issue is fixed in bootgen (PR#875808).
So reverting the commit.
This patch points to the correct readbuffer index value
in SendBankSelect API, when bank register read command
is issued for a SPANSION device in 24-bit mode.
Signed-off-by: RamyaSree <rdarapun@xilinx.com>
Acked-by: Sarat Chand Savitala <saratcha@xilinx.com>
As RSA enable and PPK revoke bits are having each 2 bits
in secure control register XilSKey_ZynqMp_EfusePs_ReadSecCtrlBits
API also returns status of 2 bits so added BOTH_BITS_SET in place
of TRUE.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
While reading secure control bits from efuse array previously
it is returning only one bit status but now modified to get
two bits of secure control bit register for RSA enable and
PPK hash revokes.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
Few IP parameters exported in smaller cases to the hdf
but the dirver tcl is checking for the same parameters in
upper case resulting wrong values are being genearted
in xparameters.h file. This patch fixes this issue.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Created a new vesrion of can can_v3_1
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Video PHY driver for abstraction of GTs.
Contribution from Gilbert Magnaye on HDMI.
Contribution from Vamsi Krishna Dhanikonda on DisplayPort.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Rohit Consul <rohitco@xilinx.com>
Compilation failure if an HDCP design was generated without a
timer counter instatiated.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Shadul Shaikh <shaduls@xilinx.com>
PHY ready check is now done immediately before initiating link
training.
In pass-through designs where the TX reference clock is derived
from the input RX clock, having no RX clock would have resulted
the TX initialization failing due to PHY ready time out.
This patch allows TX and RX to both be initialized in any
order.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Shadul Shaikh <shaduls@xilinx.com>
It is observed that when the C stack in put in TCM, ECC errors
get reported resulting in data abort.
This patch disables TCM ECC check temporarily before we come
to a proper conclusion regarding how to handle this use case.
Since we expect users to run code in R5 TCM, this patch removed
ECC check for TCMs to avoid data aborts.
Signed-off-by: Anirudha Sarangi <anirudh@xilinx.com>
Acked by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
FSBL configures the UART baud rate, MIOs and Clocks. UART init code in FW is
not fully functional and in some cases may interfere with settings done by FSBL.
So skip UART init in PMUFW to avoid conflicts.
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
Acked-by: Sarat Chand Savitala <saratcha@xilinx.com>
For sst flash parts we need to unlock global protection bits and use
bulk erase command instead of chip erase.This patch updates the same.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
For sst flash parts we need to unlock global protection bits and use
bulk erase command instead of chip erase.This patch updates the same.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acknowledge DMA transfer is complete by clearing DONE status.
This will make sure that the next transfer doesn’t assume DONE when it isn’t.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
Set speed of 1G for silicon only and run at 100Mbps on emulation platforms.
CRL_APB register configuration to 1000Mbps is also only required for silicon.
Minor comment corrections done.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Different GEM instances are present on evaluation and emulation platforms
of Zynq Ultrascale+ MPSoC.
To allow for automatic testing, select XPS_GEMx_INTR_ID based on the
PSU_<> present. Left initial definition intact for Zynq.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
This patch corrects the logic used to trigger PMU_0 IPI.
Also added code to Enable PMU_0 IPI.
Signed-off-by: RamyaSree <rdarapun@xilinx.com>
Acked-by: Sarat Chand Savitala <saratcha@xilinx.com>
This patch adds HDCP example and modifies examples, readme, index
files.
Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Acked-by: Andrei Simion <andreis@xilinx.com>
This patch adds HDCP example and modifies examples, index, readme files.
Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Acked-by: Andrei Simion <andreis@xilinx.com>
This patch integrates HDCP and Timer in DisplayPort Receiver Subsystem.
Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Acked-by: Andrei Simion <andreis@xilinx.com>
Added new lines in example prints.
Modified CRC calculation API name and
provided backward compatability.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
To program Bbram PS example is provided this example
doesnot require any input.h file it doesnot contain any control
bits to be programmed.
It has only one feature is to program AES key into BBRAM.
User can edit the macro XSK_ZYNQMP_BBRAMPS_AES_KEY with the key
to be programmed.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
To program efuse PS of Zynq MP user has to edit input.h file
in input.h file default all will be in FALSE sate which ever has to be
programmed need to be changed to TRUE.
In example after programming cache will be reloaded and keys will be
read from cache. If user wants read API can be changed to read from
efuse memory.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
Added BBRAM PS programming APIs for Zynq MP platform
In BBRAM there is no provision for saperate CRC check
CRC check can be performed only while programming AES key
So user no need to calculate CRC of key if they provide key
for programming CRC check will also be performed internally.
User can also make BBRAM key to Zero at any time.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
For ZynqMp platform's Efuse PS interface functions are added.
In efuse PS we can programm AES, User keys and PPK0, PPK1 hashs
SPK Id, JTAG user code and including some control bits.
If Tbits are not programmed some programming features can't be
programme, user no need to call any API to program this Tbits
they are programmed internally when you tried to program any
of the programming bits if Tbits are not programmed on efuse.
PPK hash accepts input in the form bootgen's hash output
user no need to change HASH.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
Modified CRC calculation API to calculate CRC of
ZynqMP efuse PS's AES CRC.
Added Ceil function to calculate ceil.
Added write and read registers APIs.
Modified Xilskey_CrcCalculation API to
XilSKey_CrcCalculation
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
