Previously, INTERRUPT_CAUSE bits 8 to 31 were being lost due to the variables
assigned having type u8.
This fix now uses masking on the interrupts as the condition to run an interrupt
handler rather than assigning the mask result to a new variable and using the
variable as a boolean condition.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Bit 21 of DPTX register PHY_CONFIG (0x200) enables 8b10b encoding.
In v6.0 of the DPTX core, the default value is '1'.
Current driver should keep this value untouched when writing to the PHY_CONFIG
register.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
It seems that monitors capable of MST, upon switching to SST mode in the monitor
options menu, respond with NACK when the segment pointer is written.
These same monitors ACK segment pointer writes when running in MST mode.
Tested monitors that are SST only monitors also ACK segment pointer writes.
The issue here is that MST monitors running in SST mode will error out when the
I2C read function is called because the segment pointer is always being written
to 0 (segment pointer is reset), and thus receives a NACK.
This patch prevents this from happening.
From now on, if the user changes the segment pointer, it is up to them to reset
it to 0.
The I2C read will only increment the segment pointer when required to do a read
outside of the base EDID block.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
For compliance, training pattern 0 should be written without using a burst write
for voltage swing and pre-emphasis values.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
For compliance purposes, training pattern 0 needs to be sent between
downshifting of lane count and link rates.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Since the RX handler initialization functions assert that the core is of type
RX, the configuration initialization function must be called prior to the
handlers being set.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Functions now assert the core context upon which they operate.
XDp_Tx* functions are meant to be used with the DisplayPort core in the TX mode
of operation.
XDp_Rx* functions are meant to be used with the DisplayPort core in the RX mode
of operation.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Rather than on the configuration structure pointer.
This makes it cleaner and easier to use as this function is an API function.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
XDp is used as an argument for all API functions. If a user application uses a
deprecated structure, it is automatically converted to the top-level XDp
structure which contains either a XDp_Tx or XDp_Rx structure which corresponds
to the previous XDptx and XDprx.
This is done for back-wards compatability with the dptx driver to minimize user
effort in migrating to the new dp driver.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
If link does not need to be re-enabled, then it is already disabled. Don't need
to disable the link again.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
If the DisplayPort core is configured for 1 or 2 maximum lanes, wait for PHY to
be ready only on those lanes rather than waiting on all 4 lanes.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Lines should not exceed 80 characters in length.
The pre-processor only replaces full names, so prefixes cannot be altered using
macros (#define XDPTX_ XDP_TX_).
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Zynq systems may have both MicroBlaze and ARM. If this is the case, assume that
the application is running on an ARM processor.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
