This patch adds coresight DCC support for Zynq Ultrascale+
MP Platform by modifying stdin and stdout range options.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This patch modifies xil-crt0.S to remove Init_Uart API call
as fsbl is initializing the UART
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies xil-crt0.S to remove Init_Uart API call
as fsbl is initializing the UART
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies Xil_DCacheFlushRange, Xil_DCacheInvalidateRange
and Xil_ICacheInvalidateRange API to add support for addresses higher
than 4GB by not truncating the addresses to 32bit
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Xil_DCacheDisable() function internally has call to Xil_DCacheFlush().
Hence removing redundant calls to Xil_DCacheFlush from FSBL.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Exception handlers are now registered unconditionally for both A53 and R5
Removed enabling of IRQ from FSBL(to be enabled in user application)
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
This patch modifies translation_table.S to put check whether
the DDR is present or not to fix the compilation error in
case of DDR-less system
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch removes xmpu, slcr, xppu header files from cortexr5 folder
and standalone tcl has been modified to copy the header files from
cortexa53/includes_ps. Makefile has been modified to include the
header files in include folder while compilation
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch creates folder 64bit to accomodate cortex-a53 64bit
mode BSP files and creates another folder includes_ps for
xmpu, xppu, slcr header files. It also changes the standalone tcl to
reflect the necessary changes
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies the check for whether bank crossover
in flash read functions for parallel case. This will fix
the bug where wrap around occurs to the top of flash when
reading very bottom..
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Check for card detection only if that signal is present
(based on HAS_CD macro)
Signed-off-by: Srinivas Goud <srinivas.goud@xilinx.com>
Signed-off-by: Harini Katakam <harinik@xilinx.com>
While creating new FSBL+BSP project, made xilsecure library
to be selected by default. This avoids compilation errors
when FSBL project is created.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
The makefile tries to detect gnu vs ARM toolchain by string-comparing
the COMPILER with some hardcoded values. This fails when the toolchain
is specified with directory components. Hence, remove directory
components from the tests.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
When authentication of partitions is not enabled, decryption is failing.
This patch fixes this issue.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
This patch does the changes in FSBL to match the signature changes of
few functions in xilsecure library.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
The pm_client.h headers hold processor specific information. Move common
information to the common header.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
swbeta2 commit 1b173007d1cc009bffeb2969a5a5bacc533647db
IPI0 is used by PMUFW for PM requests and the mask is used for determining
the Master. There are chances of IPIs being triggered before FW Init but
un-handled or even bits that are not cleared by ROM, causing a corruption
of the ISR mask. So PMUFW should cleanup these bits during startup
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
swbeta2 commit 572db0eb0f48b4f7f5684abea721c6fac92ccdee
When powering up the RPU island the individual RPU core resets as well
as the reset for the whole island are asserted. To ensure proper resume,
the island reset needs to be released when the island is powered up.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
swbeta2 commit ae6d9a98edb99ce4c51c85bce4872a9f11c7eb74
PMU Firmware is being updated to the latest code base available
in the pmufw git repo. Major changes are:
-Error Management is enabled by default
-PM Module bug fixes
-Code formatting changes
-PMU ROM handlers use ROM Table instead of
individual handler addresses
-Bug fixes in scheduler
-FW_IS_PRESENT bit is set if PM is enabled
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
swbeta2 commit 90e16f97eb510ea91702729bf38bc7c7d5d62dba
FSBL inits the TCMs that are used by R5 Apps. We have vectors in TCM-A
and that data is passed on to FSBL and it is initialized. So using the
same TCM block as vectors ensures that we use an intialized memory and
avoids ECC errors due to RMW or Reads of uninitialized memory locations.
In JTAG mode, TCM still needs to be initialized using XSDB.
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
swbeta2 commit 8e5bf013a42c56c713efcfa1ab00c78e648b2333
To ensure we resume at the correct vector address, set the VINITH bit
accordingly.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
