Modified cortexr5/gcc/Makefile to keep a correct check of a compiler
to update ECC_FLAGS correctly.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
to update ECC_FLAGS to fix a bug introduced during new version creation
of BSP
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies xil_settlbattributes API to work with
addresses > 4GB by modifying the address masking value
appropriate for higher addresses lies beyond 4GB
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
Add a separate platform file for Zynq Ultrascale MPSoC using the
respective timer and driver functions. The platform selection is
based on the processor recognized in the tcl file.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
Add support for recognizing processor A53 or R5 to work for
Zynq Ultrascale MPSoC
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
Modify makefile to check for IAR compiler to use --create and
remove individual checks for all other compilers.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch does card detection check before disk
status call, since BaseAddress and card detect
variables will be assigned in disk_status API.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
Changed the location of temporary ddr address definition.
This address is for storing PL bitstream temporarily.
User can change this address till support is provided in bootgen
(for load address configuration for PL).
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
Added checks to power up power islands, if required, before first access.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
This patch modifies the makefile for a53 to take the compiler and
archiver name from cpu tcl rather than fixing them.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies the makefile for r5 to take the compiler and
archiver name from cpu tcl rather than fixing them.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies xil_printf to add support for 64bit
pointer value print in case of 64bit mode. It adds support
to print 64 bit value for long integer and long hex.
It also removes unknown specifier 'D'.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch removes Change Bus Speed, Clock Freq, SelectCard
API's in glue layer since driver is taking care of those
things.
Signed-off-by: Srinivas Goud <sgoud@xilinx.com>
This fix stores FSBL's ATF Handoff parameters at fixed address towards
end of OCM so that ATF can avoid conflict with its sections.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
This patch modifies .mld and .tcl files to provide the
Read_Only option to the user. By default this option
is false.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch removes compilation errors in xilffs library.
This errors are coming when we configure ReadOnly, use
StringFunctions and use LFN options. This patch also does
configuring _FS_READONLY macro based on the option given
by the user.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
For SD and eMMC, BIN filenames now follow convention BOOTXXXX.BIN.
FSBL now updated as per this change.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
This patch removes compilation errors by enabling the
IntelStmFlashInitialize function for STM flash family
on DC1.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch modifies xil_mpu.c to add the API Xil_SetMPURegion
which provide the settings for a MPU region with size
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Specify the format attribute for the xil_printf() function to allow the
compiler to do printf-style checking of the format string and arguments.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Treat 'p' conversions as alias of 'x'. Strictly, not fully correct, but
better than ignoring them.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Treat 'X' conversions as alias of 'x'. Strictly, that is not fully
correct, but still better than ignoring them.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
This patch adds coresight DCC support for Zynq Ultrascale+
MP Platform by modifying stdin and stdout range options.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This patch modifies xil-crt0.S to remove Init_Uart API call
as fsbl is initializing the UART
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies xil-crt0.S to remove Init_Uart API call
as fsbl is initializing the UART
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies Xil_DCacheFlushRange, Xil_DCacheInvalidateRange
and Xil_ICacheInvalidateRange API to add support for addresses higher
than 4GB by not truncating the addresses to 32bit
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
