Commit graph

943 commits

Author SHA1 Message Date
Andrei-Liviu Simion
fc4dca3846 dp: rx: Updated timer usage in examples.
Set the reset value for the timer upon initialization.
Use the timer ID as an argument for consistency with the other
device IDs.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
2015-08-05 21:11:28 +05:30
Andrei-Liviu Simion
29952963ce dp: rx: Add DP159 dependencies to initialization.
Using the DP159 solution, 8 ms needs to be used as the AUX training
interval.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
2015-08-05 21:10:05 +05:30
Andrei-Liviu Simion
513926d80a dp: rx: Added macros for the training settings and CDR control.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
2015-08-05 21:09:12 +05:30
Andrei-Liviu Simion
8518d9a3da dp: rx: Optimized initialization.
RX initialization is not dependent on PLL and reset checks.
- Training will not be initiated until the RX is ready.

The clock is transmitted only once the cable is connected.
- This means that the CPLLs will never lock if no cable is plugged
in resulting in DP RX core initialization time out.

Moved core and interrupt mask enables towards end of function.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
2015-08-05 21:08:46 +05:30
Andrei-Liviu Simion
3b39183e40 video_common: Updated version to v2.0.
Due to DP159 API additions.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
2015-08-05 21:06:08 +05:30
VNSL Durga
7ca1fb1844 xilskey: Modified example and input.h files
Example has been modified to support both Zynq PL eFuse and
Ultrascale eFuse. Added GPIO pins and channels to access
Master Jtag through GPIO and RSA key hash, AES's CRC value
input macros are also added.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-08-05 21:05:52 +05:30
VNSL Durga
02ccf03a94 xilskey: Added ultrascale efuse functionality
Added macros and functions required for accessing
Ultrascale's eFuse

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-08-05 21:05:39 +05:30
VNSL Durga
0b14b181ba xillskey: Added new functions
As GpioPs and Timers are different for Ultrascale
all the calls related to Gpio and timers are saperated
by ifdefinitions.
Added new jtag function to access efuse of Ultrascale.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-08-05 21:05:24 +05:30
VNSL Durga
365de9549f xilskey: Modified PL instance.
To add ultrascale's efuse functionality added GPIO pins
and GPIO channels to access master JTAG, Fpga_Flag to tell
the FPGA series, AES CRC check flag and AES CRC value, RSA key
hash to program and RSA key hash read back and control and
secure parameters in PL instance and modified IR length
macro ZYNQ_TAP_IR_LENGTH to TAP_IR_LENGTH as IR length is same for both
Zynq and Ultrasale.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-08-05 21:05:07 +05:30
VNSL Durga
00e045e760 xilskey:Added API for clk calculations.
Removed redundant code by adding common API for clock
calculations.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-08-05 21:04:48 +05:30
VNSL Durga
e2ccad3c90 xilskey: Modified xilskey_efuse_example
Modified macro name of efuse PS XSK_EFUSEPL_RSA_KEY_HASH_STRING_SIZE
to XSK_EFUSEPS_RSA_KEY_HASH_STRING_SIZE.
Added missing goto.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-08-05 21:04:35 +05:30
VNSL Durga
841227f998 xilskey: Added new version v3_0
Modified tcl for adding macro in xparameters.h based on the
processor.As support is being added for Ultrascale and hence
supported processors are a9 and microblaze too, removed
supported peripherals option in mld.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-08-05 21:03:24 +05:30
Bhavik Ameta
d27a264328 sw_services:xilsecure: Changed RSA API error codes
RSA sign verification error codes combined into XST_FAILURE.

Signed-off-by: Bhavik Ameta <bameta@xilinx.com>
Acked-by: Sarat Chand Savitala <saratcha@xilinx.com>
2015-08-04 18:05:10 +05:30
Bhavik Ameta
976c6455ad sw_services:xilsecure: Pointer warnings fixed
Changed u64 casts to UINTPTR, to fix the warnings.

Signed-off-by: Bhavik Ameta <bameta@xilinx.com>
Acked-by: Sarat Chand Savitala <saratcha@xilinx.com>
2015-08-04 18:05:01 +05:30
Bhavik Ameta
2491b4d9a2 sw_services:xilsecure: R5 build failure fixed
Removed individual checks for compilers from Makefile.These were causing build failure.

Signed-off-by: Bhavik Ameta <bameta@xilinx.com>
Acked-by: Sarat Chand Savitala <saratcha@xilinx.com>
2015-08-04 18:04:29 +05:30
Rohit Consul
eff8fdf3f3 vprocss: Added vdma alignment fix
-Added logic to fix vdma ip alignement issues with different bit
 width at axis and aximm interface at all supported pixel/clk
 and color depth combinations
-Moved stream (input/output) validation logic scattered around
 in different blocks to a central location
-Added API to report subsystem configuration status
-Code cleanup and changed relevant prints to dbg print

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
2015-08-04 14:11:50 +05:30
Rohit Consul
759573e90f v_hscaler: Bug Fix in phase calculation logic
4 Samples/Clock phase calculation logic works on 64bit entities.
However a 32bit variable was used that caused wrong phase
information to be generated. Updated relevant variables to 64b

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
2015-08-04 14:11:38 +05:30
Rohit Consul
b015782fbc vprocss: Added subcores support for mutiple pixel/clk
- Code cleanup to remove interrupt handler registration.
   Subsystem does not have interrupts
 - Updated sub-core init routines to load default filter
   coefficients for scaler and chroma resamplers
 - Added layer 2 registers for chroma resamplers
 - Updated VDMA Read/Write interface to work with color depth
   instead of Bytes/Pixel

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
2015-08-04 14:11:07 +05:30
Rohit Consul
f4901fa438 v_vscaler: Added multiple pixel per clock support
- IP updated to add multiple pixel/clk support.
 - Added default filter coefficient table for 6/8/10/12 taps
 - Added API to load default coefficients or allow user to load
   externally defined coefficients
 - Peformed code cleanup to remove coefficient generation logic
   (scaler to use fixed coefficients)

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
2015-08-04 14:10:51 +05:30
Rohit Consul
5fb5067657 v_vcresampler: Added default filter coefficients
-Added filter coefficient table for 4/6/8/10 taps.
 -Added API to load the default coefficients
 -Added API to allow user to load coefficients

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
2015-08-04 14:10:44 +05:30
Rohit Consul
0e0a006e7b v_tpg: Add copyright information to mdd
Added Xilinx copyright header to mdd file

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
2015-08-04 14:10:37 +05:30
Rohit Consul
fb2d56f8c9 v_letterbox: Add copyright info to mdd
Added xilinx copyright information to mdd

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
2015-08-04 14:10:30 +05:30
Rohit Consul
4955188410 v_hscaler: Added multiple pixel per clock support
- IP updated to add multiple pixel/clk support.
- Added default filter coefficient table for 6/8/10/12 taps
- Added API to load default coefficients or allow user to load
  externally defined coefficients
- Peformed code cleanup to remove coefficient generation logic
  (scaler to use fixed coefficients)

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
2015-08-04 14:10:22 +05:30
Rohit Consul
4054a7aa4e v_hcresampler: Added default filter coefficients
-Added filter coefficient table for 4/6/8/10 taps.
-Added API to load the default coefficients
-Added API to allow user to load coefficients

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
2015-08-04 14:10:12 +05:30
Rohit Consul
533b4d0587 v_deinterlacer: Add multiple samples per clock support
IP updated to add multiple pixels per clock support resulting in
API changes in driver.

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
2015-08-04 14:10:04 +05:30
Rohit Consul
7ab5756f84 v_csc: Add copyright info
This patch adds copyright info to HLS generated mdd file

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
2015-08-04 14:09:55 +05:30
Nava kishore Manne
7a47ffd9e8 Removed executable file permission from source code files.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Acked-by: Anirudha Sarangi   <anirudh@xilinx.com>
2015-08-03 18:32:57 +05:30
Kedareswara rao Appana
93b8d7f2f5 lwip: remove unnessary code check in tcl
This patch removes the unnecessary check in the lwip tcl
it is causing the compilation issues in few ethernetlite based designs.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Anirudha Sarangi   <anirudh@xilinx.com>
2015-08-03 18:32:01 +05:30
Sarat Chand Savitala
4968e7c610 sw_apps:zynqmp_fsbl: Updated watchdog code for JTAG bootmode
As in JTAG bootmode, watchdog is not initialized, avoided stopping of
watchdog in JTAG bootmode.

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
2015-08-03 14:55:49 +05:30
P L Sai Krishna
ad401f70a5 sdps: Used MB_Sleep API for microblaze.
This patch use MB_Sleep API for microblaze design
and removed sleep.h inclusion in xsdps.h file.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-08-03 14:32:32 +05:30
Sarat Chand Savitala
dff2a597f9 sw_apps:zynqmp_fsbl: Added watchdog support
This patch adds System Watchdog Timer support

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
2015-08-02 21:27:53 +05:30
Harini Katakam
4ceb19f1ae emacps: Do not call error handler with an error code zero
BUFFNA is not an error and hence the status bit is cleared by the
driver. But the error handler callback is called with a zero error
code in this case. Correct the same.

Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
2015-08-02 21:27:20 +05:30
P L Sai Krishna
09cd729c86 xilffs: Used --create option for armcc compiler.
This patch use --create option for armcc compiler
instead of rc option.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-07-31 16:56:24 +05:30
Suneel Garapati
15a5404a04 Thirdparty: bsp: freeRTOS support for all architectures
add freeRTOS bsp to support microblaze, cortexa9 and cortexr5
architectures for respective platforms.

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Acked-by: Anirudha Sarangi   <anirudh@xilinx.com>
2015-07-31 16:56:23 +05:30
Kinjal Pravinbhai Patel
60c693e0fe bsp: added support for 32bit bsp for A53
This patch modifies standalone bsp tcl to generate 32bit/64bit
a53 bsp by keeping compiler check in the tcl to copy the
appropriate source file while generating standalone bsp

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi   <anirudh@xilinx.com>
2015-07-31 16:56:22 +05:30
Sarat Chand Savitala
e1dd360db8 sw_apps:zynqmp_fsbl: Code cleanup involving emulation platforms
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
2015-07-31 16:56:20 +05:30
RamyaSree
8dc4f9e7fd sw_apps: zynqmp_fsbl: Modified bus width in dummy phase.
This patch modifies the buswidth in dummy phase as
in data phase.

Signed-off-by: RamyaSree <rdarapun@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-07-31 16:56:19 +05:30
RamyaSree
8e402be829 sw_apps: zynqmp_fsbl: enabled cache for qspipsu boot.
This patch enables cache for qspipsu boot.

Signed-off-by: RamyaSree <rdarapun@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-07-31 16:56:19 +05:30
RamyaSree
6f67bc7850 sw_apps: zynqmp_fsbl: added Tx/Rx Flags in qspi message format
This patch added Tx/Rx flags in qspi message format
according to qspipsu driver changes.

Signed-off-by: RamyaSree <rdarapun@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-07-31 16:56:18 +05:30
Soren Brinkmann
731fcf06db xilsecure: Fix make rules
When building xilsecure with '-rR' as arguments to make causes this error:
  Compiling Xilsecure Library
  make[1]: *** No rule to make target 'xsecure_sha.o', needed by 'libxilsecure.a'.  Stop.
  Makefile:27: recipe for target 'psu_cortexa53_0/libsrc/xilsecure_v1_0/src/make.libs' failed
  make: *** [psu_cortexa53_0/libsrc/xilsecure_v1_0/src/make.libs] Error 2

Fixing this by adding a pattern rules matching the required object files.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Bhavik Ameta <bameta@xilinx.com>
2015-07-31 16:56:17 +05:30
Soren Brinkmann
c8bca6ce1a xilsecure: Remove dead code
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Bhavik Ameta <bameta@xilinx.com>
2015-07-31 16:56:16 +05:30
Nava kishore Manne
a5ca97dccf Fix for iomodule os tcl to support MultiBd and Packaged Bd
Acked-for-series: Naga Sureshkumar Relli <nagasure@xilinx.com>
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
2015-07-31 16:56:16 +05:30
Nava kishore Manne
cabafea458 Fix for standalone os tcl to support MultiBd and Packaged Bd
Acked-for-series: Naga Sureshkumar Relli <nagasure@xilinx.com>
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
2015-07-31 16:56:15 +05:30
Nava kishore Manne
a96825c608 Fix for xilikernel os tcl to support MultiBd and Packaged Bd
Acked-for-series: Naga Sureshkumar Relli <nagasure@xilinx.com>
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
2015-07-31 16:56:15 +05:30
Kedareswara rao Appana
416cbc369b axiethernet: Fix bug in the driver tcl when axi ethernet is configured with fifo
This patch fixes the issue AXI Ethernet with FIFO will fail to
create the BSP if the interrupt pin on the FIFO is unconnected.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Anirudha Sarangi   <anirudh@xilinx.com>
2015-07-31 16:56:14 +05:30
Kedareswara rao Appana
436240a4f7 lwip: Add support for axi ethernet with fifo on zynq
This patch adds lwip support for the axi ethernet with fifo
combination on zynq.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Anirudha Sarangi   <anirudh@xilinx.com>
2015-07-31 16:56:13 +05:30
Punnaiah Choudary Kalluri
c46210930c nandpsu: Convert the three line comments to single line
This patch converts the three line comments to single line

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acked-by: Anirudha Sarangi   <anirudh@xilinx.com>
2015-07-31 16:56:13 +05:30
Punnaiah Choudary Kalluri
30c8402cdc nandpsu: Remove redundant code
This patch adds common routines by removing the possible redundant
code from the functions.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acked-by: Anirudha Sarangi   <anirudh@xilinx.com>
2015-07-31 16:56:12 +05:30
Punnaiah Choudary Kalluri
fb124d3372 nandpsu: Decrease the XNANDPSU_MAX_BLOCKS value
This change is to reduce the size of the static bbt table size
from 8KB to 4KB because so far we have not identified the
flash part that has more than 16K blocks and also it will
reduce the bsp size.

Driver warns if the device has more number of blocks than the
defined value so that this can be incremented in future and if
there is a part available.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acked-by: Anirudha Sarangi   <anirudh@xilinx.com>
2015-07-31 16:56:11 +05:30
Punnaiah Choudary Kalluri
ac89dc0908 nandpsu: Remove NO_OOB option for bbt
As per the csurom, Bbt signature is always stored in oob area.
So, to sync with csurom, removing the NO_OOB(Bbt signature stores
in page area) functionality.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acked-by: Anirudha Sarangi   <anirudh@xilinx.com>
2015-07-31 16:56:11 +05:30