1
0
Fork 0
mirror of https://git.rwth-aachen.de/acs/public/villas/node/ synced 2025-03-16 00:00:02 +01:00
Commit graph

581 commits

Author SHA1 Message Date
f59a763cd1 Merge branch 'fix-cmake' into 'master'
cmake: allow linking libxil from non-standard location

See merge request acs/public/villas/fpga/fpga!15
2020-11-12 00:45:06 +01:00
2bbe5bc0ab cmake: allow linking libxil from non-standard location 2020-11-12 00:19:55 +01:00
a04c1d7abf ci: add cppcheck 2020-09-21 09:37:10 +02:00
5502d3577b remove unused submodules 2020-08-17 17:21:18 +02:00
8ec16094f2 fix code-style 2020-07-27 16:48:53 +02:00
e5545aa17e emc: add initial code to flash FPGA bitstream via PCIe 2020-07-08 17:16:43 +02:00
eabae63714 update submodules 2020-07-08 15:24:01 +02:00
08114652d6 emc: add stub IP 2020-07-08 15:20:05 +02:00
10b8878279 fix naming of factories 2020-07-08 15:10:26 +02:00
8bb033f89d update hardware submodule and move hwdef-parse script into hardware repo 2020-07-08 14:14:38 +02:00
Hatim Kanchwala
8a4e95d75c Use sensible colour scheme for error status output 2020-07-04 15:11:01 +02:00
Hatim Kanchwala
89f75c9a57 Remove old JSON config files 2020-07-04 15:11:00 +02:00
c4fe7e4b07 update libxil submodule 2020-06-15 22:49:43 +02:00
ba9d670d4b cmake: make unit-tests optional 2020-06-15 22:49:19 +02:00
7e2365bfa0 ci: update CI config 2020-06-15 22:09:18 +02:00
031311ba95 docker: add missing deps 2020-06-15 21:45:50 +02:00
a935a5856a docker: add mising ssl headers 2020-06-15 21:29:46 +02:00
2700493f2f docker: fix location of FEIN e.V. repo 2020-06-15 21:25:55 +02:00
c5e3d3dd4a node: add connect() with reverse path 2020-06-15 21:21:16 +02:00
6c225c8fae update VILLAScommon submodule 2020-06-15 21:21:05 +02:00
74f55fa98c refactor: more code-style improvements 2020-06-15 21:08:49 +02:00
cc456b6525 refactor: no namespace scopes in source files 2020-06-14 22:12:41 +02:00
d938bd95b1 cmake: fixups for inclusion into VILLASnode 2020-06-14 22:11:58 +02:00
a9f9dc4a37 refactor: no namespace scoeps in source files 2020-06-14 22:11:26 +02:00
8b7bbe27c6 refactor: whitespaces for references 2020-06-14 22:03:50 +02:00
e86a291dfd update VILLAScommon submodule 2020-06-12 00:08:04 +02:00
6b3164dd26 refactor IpNode and IpCore class names 2020-06-12 00:05:03 +02:00
7c92a30ab4 several cleanups and bugfixes 2020-06-11 23:55:05 +02:00
bb8a711f02 use new getter for graph 2020-06-11 23:40:12 +02:00
1af96b20e4 pipe: use correct DMA instance 2020-06-11 19:02:49 +02:00
b7e5bfead2 harmonize codestyle 2020-06-11 18:38:46 +02:00
3f1ab8e862 use new vlnv id for aurora_axis 2020-06-11 18:19:28 +02:00
77b55f65f7 use new plugin mechanism 2020-06-11 18:19:03 +02:00
91f9000038 unit-tests: allow FPGA configuration to provided via env var 2020-06-11 16:09:58 +02:00
cc1d1d4298 plugin: fix lookup 2020-06-11 16:01:42 +02:00
86f8997b05 gpio: add new IP for AXI programmable GPIO 2020-06-11 15:58:02 +02:00
d5b1012b75 intc: fix name of register space 2020-06-11 15:57:05 +02:00
6882e9d418 harmonize code-style with VILLAScommon/node 2020-06-11 14:26:38 +02:00
c906116d86 update to latest VILLAScommon submodule 2020-06-11 14:20:33 +02:00
3b28eea7d2 aurora_axis: add two functions to reset counters and configure loopback mode 2020-06-11 13:08:42 +02:00
1596208bb6 aurora_axis: dump frame counters 2020-06-11 13:01:44 +02:00
3d15323376 aurora_axis: harmonize with HDL changes 2020-06-11 13:01:27 +02:00
bab9e22fdb update submodule urls 2020-06-11 12:37:53 +02:00
Hatim Kanchwala
448068082f Improve comments for status/control register bits 2020-06-08 00:55:33 +02:00
Hatim Kanchwala
0a7c6cc31c Define register addresses and bits 2020-06-05 23:41:08 +02:00
Hatim Kanchwala
4005a0b40e Merge branch 'master' of git.rwth-aachen.de:acs/public/villas/VILLASfpga 2020-06-02 00:54:54 +02:00
Hatim Kanchwala
bf67a2e5f0 Add initial Aurora driver 2020-06-02 00:54:31 +02:00
02f60eb86e add a writeMemory function to IpCore class 2020-05-26 15:24:15 +02:00
Hatim Kanchwala
73e85f2e5a Add intial header file for Aurora 2020-05-26 14:46:35 +02:00
dd1a17c4a5 update bitstream configs 2019-08-15 13:57:29 +02:00