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f59a763cd1
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Merge branch 'fix-cmake' into 'master'
cmake: allow linking libxil from non-standard location
See merge request acs/public/villas/fpga/fpga!15
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2020-11-12 00:45:06 +01:00 |
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2bbe5bc0ab
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cmake: allow linking libxil from non-standard location
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2020-11-12 00:19:55 +01:00 |
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a04c1d7abf
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ci: add cppcheck
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2020-09-21 09:37:10 +02:00 |
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5502d3577b
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remove unused submodules
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2020-08-17 17:21:18 +02:00 |
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8ec16094f2
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fix code-style
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2020-07-27 16:48:53 +02:00 |
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e5545aa17e
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emc: add initial code to flash FPGA bitstream via PCIe
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2020-07-08 17:16:43 +02:00 |
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eabae63714
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update submodules
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2020-07-08 15:24:01 +02:00 |
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08114652d6
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emc: add stub IP
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2020-07-08 15:20:05 +02:00 |
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10b8878279
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fix naming of factories
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2020-07-08 15:10:26 +02:00 |
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8bb033f89d
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update hardware submodule and move hwdef-parse script into hardware repo
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2020-07-08 14:14:38 +02:00 |
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Hatim Kanchwala
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8a4e95d75c
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Use sensible colour scheme for error status output
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2020-07-04 15:11:01 +02:00 |
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Hatim Kanchwala
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89f75c9a57
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Remove old JSON config files
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2020-07-04 15:11:00 +02:00 |
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c4fe7e4b07
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update libxil submodule
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2020-06-15 22:49:43 +02:00 |
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ba9d670d4b
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cmake: make unit-tests optional
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2020-06-15 22:49:19 +02:00 |
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7e2365bfa0
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ci: update CI config
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2020-06-15 22:09:18 +02:00 |
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031311ba95
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docker: add missing deps
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2020-06-15 21:45:50 +02:00 |
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a935a5856a
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docker: add mising ssl headers
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2020-06-15 21:29:46 +02:00 |
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2700493f2f
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docker: fix location of FEIN e.V. repo
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2020-06-15 21:25:55 +02:00 |
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c5e3d3dd4a
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node: add connect() with reverse path
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2020-06-15 21:21:16 +02:00 |
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6c225c8fae
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update VILLAScommon submodule
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2020-06-15 21:21:05 +02:00 |
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74f55fa98c
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refactor: more code-style improvements
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2020-06-15 21:08:49 +02:00 |
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cc456b6525
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refactor: no namespace scopes in source files
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2020-06-14 22:12:41 +02:00 |
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d938bd95b1
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cmake: fixups for inclusion into VILLASnode
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2020-06-14 22:11:58 +02:00 |
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a9f9dc4a37
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refactor: no namespace scoeps in source files
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2020-06-14 22:11:26 +02:00 |
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8b7bbe27c6
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refactor: whitespaces for references
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2020-06-14 22:03:50 +02:00 |
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e86a291dfd
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update VILLAScommon submodule
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2020-06-12 00:08:04 +02:00 |
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6b3164dd26
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refactor IpNode and IpCore class names
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2020-06-12 00:05:03 +02:00 |
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7c92a30ab4
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several cleanups and bugfixes
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2020-06-11 23:55:05 +02:00 |
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bb8a711f02
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use new getter for graph
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2020-06-11 23:40:12 +02:00 |
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1af96b20e4
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pipe: use correct DMA instance
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2020-06-11 19:02:49 +02:00 |
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b7e5bfead2
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harmonize codestyle
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2020-06-11 18:38:46 +02:00 |
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3f1ab8e862
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use new vlnv id for aurora_axis
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2020-06-11 18:19:28 +02:00 |
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77b55f65f7
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use new plugin mechanism
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2020-06-11 18:19:03 +02:00 |
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91f9000038
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unit-tests: allow FPGA configuration to provided via env var
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2020-06-11 16:09:58 +02:00 |
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cc1d1d4298
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plugin: fix lookup
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2020-06-11 16:01:42 +02:00 |
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86f8997b05
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gpio: add new IP for AXI programmable GPIO
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2020-06-11 15:58:02 +02:00 |
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d5b1012b75
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intc: fix name of register space
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2020-06-11 15:57:05 +02:00 |
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6882e9d418
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harmonize code-style with VILLAScommon/node
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2020-06-11 14:26:38 +02:00 |
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c906116d86
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update to latest VILLAScommon submodule
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2020-06-11 14:20:33 +02:00 |
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3b28eea7d2
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aurora_axis: add two functions to reset counters and configure loopback mode
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2020-06-11 13:08:42 +02:00 |
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1596208bb6
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aurora_axis: dump frame counters
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2020-06-11 13:01:44 +02:00 |
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3d15323376
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aurora_axis: harmonize with HDL changes
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2020-06-11 13:01:27 +02:00 |
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bab9e22fdb
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update submodule urls
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2020-06-11 12:37:53 +02:00 |
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Hatim Kanchwala
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448068082f
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Improve comments for status/control register bits
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2020-06-08 00:55:33 +02:00 |
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Hatim Kanchwala
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0a7c6cc31c
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Define register addresses and bits
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2020-06-05 23:41:08 +02:00 |
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Hatim Kanchwala
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4005a0b40e
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Merge branch 'master' of git.rwth-aachen.de:acs/public/villas/VILLASfpga
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2020-06-02 00:54:54 +02:00 |
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Hatim Kanchwala
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bf67a2e5f0
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Add initial Aurora driver
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2020-06-02 00:54:31 +02:00 |
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02f60eb86e
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add a writeMemory function to IpCore class
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2020-05-26 15:24:15 +02:00 |
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Hatim Kanchwala
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73e85f2e5a
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Add intial header file for Aurora
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2020-05-26 14:46:35 +02:00 |
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dd1a17c4a5
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update bitstream configs
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2019-08-15 13:57:29 +02:00 |
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