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6285 commits 172 branches 31 tags 76 MiB
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191 commits

Author SHA1 Message Date
Niklas Eiling
cee5f62c2d fpga: remove exceptions from AxisCache 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2025-01-24 10:32:57 +01:00
Niklas Eiling
5dd12eafc4 fpga: Apply suggestions from code review 
Co-authored-by: Steffen Vogel <steffen.vogel@opal-rt.com>
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2025-01-24 10:32:57 +01:00
Niklas Eiling
0d6946bae9 fpga/ip/i2c: remove dead code and improve comment. 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2025-01-24 10:32:57 +01:00
Niklas Eiling
e9b1a4a528 fpga: improve comments 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2025-01-24 10:32:57 +01:00
Niklas Eiling
a7427d7cc0 fpga/ips: add invalidate method to AxisCache and whitelist the IP in hwdef-parse.py 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2025-01-24 10:32:57 +01:00
Niklas Eiling
ce0959d4ba fpga: Clean up dino.cpp 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2025-01-24 10:32:57 +01:00
Niklas Eiling
afcfe08576 fpga: Fix I2c causing an error when Dino FMC is not connected. We loose the self check, but this is not really possible if there is no Dino FMC. 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2025-01-24 10:32:57 +01:00
Niklas Eiling
bf2b18bf47 fpga: Add new Dino configuration register that allows triggering the DAC before the time step to dino.cpp 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2025-01-24 10:32:57 +01:00
Niklas Eiling
6b0b11e720 fpga: Add driver for new register interface of axis cache IP 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2025-01-24 10:32:57 +01:00
Niklas Eiling
eeeb9b1d7b dino: fix wrong copyright notice in dino.cpp 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-08-26 10:09:01 +02:00
Niklas Eiling
f25e1dd689 log: fix undefined intitialization order of static objects. fixes #799. 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-08-05 14:57:13 +02:00
Niklas Eiling
5f44e16ced fpga: remove dead code and improve comments in Dino IP 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-07-29 13:50:36 +02:00
Niklas Eiling
7128da24c3 fpga: make dma able to handle sequence numbers generated in the FPGA 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-07-29 13:50:36 +02:00
Niklas Eiling
136d033cd3 fpga: fix dino setting wrong offset value to float converter 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-07-29 13:50:36 +02:00
Niklas Eiling
7991d31393 fpga/dino: add and set new registers 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-07-29 13:50:36 +02:00
Niklas Eiling
aeda901e47 fpga: use separate locks for write and read to allow them to be used concurrently 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-06-05 12:30:24 +02:00
Niklas Eiling
973834b3aa fpga: use constants to access registers 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-05-29 09:18:00 +02:00
Niklas Eiling
0c3a9f4729 fpga: convert SignalType to string before printing 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-05-29 09:18:00 +02:00
Niklas Eiling
12af65b2b4 fpga: move register config for dino to DinoAdc 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-05-29 09:18:00 +02:00
Niklas Eiling
ed05671a51 fpga: improve comments in register.cpp 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-04-19 10:09:47 +02:00
Niklas Eiling
c151be5cca fpga: fix includes and various comments 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-04-19 10:09:47 +02:00
Niklas Eiling
f1776f8be4 fpga: improve comments for fastRead and fastWrite 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-04-19 10:09:47 +02:00
Niklas Eiling
2cc8cad115 fpga: expose methods for finer control over DMA data path 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-04-19 10:09:47 +02:00
Niklas Eiling
248a4b3a0d fpga: improve dma latency 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-04-19 10:09:47 +02:00
Niklas Eiling
483293aec8 fpga: turn off all interrupts when using polling 
this improves the latency by at least 4 us in my setup.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-04-19 10:09:47 +02:00
Niklas Eiling
57d7396c09 fpga: optimize sg descriptor rings 
we are now using only one memory block for both sg rings. This is
required so that the SG interface can benefit from a read cache

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-04-19 10:09:47 +02:00
Niklas Eiling
c644c8f630 fpga: DMA: poll BD instead of hardware register 
polling HW is slow (>1us). Polling RAM is faster. This is a first implementation which only polls the first BD that is active. This is why this commit also removes the second read in nodes/fpga. This is not really useful anyways.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-03-14 16:07:45 +01:00
Niklas Eiling
ca03e1d406 fpga: enable using Xilinx xdma IP as DMA to AXI bridge as required for Ultrascale+ FPGAs 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-03-14 16:07:45 +01:00
Niklas Eiling
7f1fe8f742 fpga: default Dino rate should be 20kHz 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-03-14 16:07:45 +01:00
Steffen Vogel
dc436073a2 Use spaces for indention of C++ comments 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2024-02-29 23:18:47 +01:00
Steffen Vogel
3d73c759ea Reformat all code with clang-format 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2024-02-29 19:34:27 +01:00
Niklas Eiling
033634ac47 register: ignore strict aliasing for setting register as float 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-26 15:39:27 +01:00
Niklas Eiling
a3209aa344 use polling instead of interrupt 
but keep interrupts for i2c

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-26 11:50:44 +01:00
Niklas Eiling
d588f5f2a2 dino: use enum instead of literal for GAIN 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-26 11:50:44 +01:00
Niklas Eiling
fb742dddd1 register: increase register num to 8 
the VHDL changed so we need to change register here too

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-26 11:50:44 +01:00
Niklas Eiling
ee068621e6 ips/register: add default config for Dino 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-14 14:20:33 +01:00
Niklas Eiling
d54e4eb3f0 ips/register: add IP for the new register interface 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-14 14:20:33 +01:00
Niklas Eiling
1bb6c221f6 ips/dma: fix memory leak in libxil code by explicitly calling free on 
CyclicBd

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-14 14:20:33 +01:00
Niklas Eiling
c730412e98 ips/intc: move deinit to stop instead of destructor 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-14 14:20:33 +01:00
Niklas Eiling
2c72af935a ips/i2c: move deinit to stop instead of destructor 
accessing register space from destructor can cause use after free errors

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-14 14:20:33 +01:00
Niklas Eiling
6e1783612d ips/intc: remove access to xilinx driver in case we are using VFIO 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-07 18:21:45 +01:00
Niklas Eiling
d6fd533f0c ips/dma: make interrupt handling more robust 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-07 18:21:45 +01:00
Niklas Eiling
e505bfb5d9 ips/dma: reformat and make more robust 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-07 18:21:45 +01:00
Niklas Eiling
f2db38fe44 ip/switch: reformat and add function that prints current switch config 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-07 18:21:45 +01:00
Niklas Eiling
7c6d350eb0 format and increase robustness of interuppt handling 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-07 18:21:45 +01:00
Niklas Eiling
8b95182b08 automatically configure and test Dino based on hwdef json 
this currently requires manually adding the mapping of Dinos to i2c
buses in the fpga json.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
b5682290c2 I2c: use Switch::selfTest to check i2c bus 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
d4a868ae7c Dino: add debug output for direction registers of io extender 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
db062f08bd Dino: overload operator>> for IoextPorts 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
60c65c2880 verify more assumptions in i2c 
add selftest to I2c and readback Dino configuration to verify it was
actually set

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00