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28 commits

Author SHA1 Message Date
Niklas Eiling
ca03e1d406 fpga: enable using Xilinx xdma IP as DMA to AXI bridge as required for Ultrascale+ FPGAs
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-03-14 16:07:45 +01:00
3d73c759ea Reformat all code with clang-format
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 19:34:27 +01:00
Steffen Vogel
157d5b21d7 Make REUSE copyright notice the same as in other VILLASframework projects and fix comments (#82)
This edits the headers in every file so the copyright notice mentions RWTH Aachen University. We also update some copyright years and fix various comments so the header is the same across all of VILLASframework.

* Harmonize comment and code-style

Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>

* Harmonize comment and code-style

Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>

---------

Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2023-09-08 11:35:18 +02:00
Pascal Henry Bauer
3587ccc0fa change pciecard name to pcie_card
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
2023-01-26 18:30:14 +01:00
Pascal Henry Bauer
6b87c9bc30 refactor to use pcie card (Legacy)
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
2023-01-26 18:30:14 +01:00
9b27c31b9c fixup copyright texts
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-01-07 17:32:48 +01:00
f776cba693 relicense project to Apache 2.0
The project is now also REUSE compliant: https://reuse.software/
Previous copyright holders have provided their
acknowledgement to transition to the new license in the
following GitHub PR: https://github.com/VILLASframework/fpga/pull/66

Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-01-07 17:20:15 +01:00
53ddbe4e10 refactor registration of IP core drivers to be aligned with registration of VILLASnode formats and node-types
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-01-05 14:21:20 +01:00
c2437b51cf smaller code-style fixes
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2022-12-05 09:35:33 +01:00
09af6d9e88 refactor Core::configure() to Core::parse()
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2022-12-05 09:35:32 +01:00
14c7e57a8a fix parsing of IP parameters
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2022-12-05 09:35:32 +01:00
0e0197a3be fix coding style 2022-10-28 08:03:57 -04:00
9ef01d068e update year in copyright notices 2022-08-30 12:22:40 -04:00
fb824a82f9 cleanup of comments 2022-08-30 12:21:46 -04:00
6c225c8fae update VILLAScommon submodule 2020-06-15 21:21:05 +02:00
74f55fa98c refactor: more code-style improvements 2020-06-15 21:08:49 +02:00
a9f9dc4a37 refactor: no namespace scoeps in source files 2020-06-14 22:11:26 +02:00
8b7bbe27c6 refactor: whitespaces for references 2020-06-14 22:03:50 +02:00
6b3164dd26 refactor IpNode and IpCore class names 2020-06-12 00:05:03 +02:00
7c92a30ab4 several cleanups and bugfixes 2020-06-11 23:55:05 +02:00
b7e5bfead2 harmonize codestyle 2020-06-11 18:38:46 +02:00
Daniel Krebs
93fe1390d6 fix wrong usage of reinterpret_cast in ips and tests 2018-06-04 17:36:36 +02:00
Daniel Krebs
5097827757 fix include paths, use <villas/...> style 2018-06-04 13:24:57 +02:00
Daniel Krebs
f644a9faa8 ips/pcie: move BAR0 mapping from card into PCIe IP 2018-05-15 18:04:24 +02:00
Daniel Krebs
89b5169a6e ips/pcie: parse AXI/PCI BARs and create mappings to/from PCIe address space
This is used for translations that don't use VFIO which used to bridge
the PCIe address space by creating direct mappings from process VA to
the FPGA. When we want to communicate directly via PCIe without the
involvment of the CPU/VFIO, we need the proper translations that are
configured in the FPGA hardware.
2018-05-15 18:04:24 +02:00
Daniel Krebs
60882f1086 lib/memory: implement memory handling with allocators and blocks
This commit is 2/2 of a series of patches and not working on its own.
2018-03-26 16:17:20 +02:00
Daniel Krebs
aa2b0b324f lib/ips/pcie: use cached address space id and supply interface to create mapping 2018-02-14 14:34:03 +01:00
Daniel Krebs
e93b31bbf1 lib/ips: make use of MemoryManager and new config layout 2018-02-14 07:28:25 +01:00