Pascal Henry Bauer
7534086e08
change core to use base class card over pcieclass
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Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
2023-01-26 18:30:14 +01:00
9b27c31b9c
fixup copyright texts
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-01-07 17:32:48 +01:00
f776cba693
relicense project to Apache 2.0
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The project is now also REUSE compliant: https://reuse.software/
Previous copyright holders have provided their
acknowledgement to transition to the new license in the
following GitHub PR: https://github.com/VILLASframework/fpga/pull/66
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-01-07 17:20:15 +01:00
53ddbe4e10
refactor registration of IP core drivers to be aligned with registration of VILLASnode formats and node-types
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2023-01-05 14:21:20 +01:00
dee5b2d81f
update Steffens mail address
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2022-12-14 17:44:17 +01:00
92ab5d078f
remove aliases for smart pointers and lists
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2022-12-07 19:04:47 +01:00
Niklas Eiling
03f8d0782e
Revert "core: move configuration of polling mode to parse()"
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The changes lead to crashing because intc will not be configured
properly. Also revert removing configDone in ips/dma
This reverts commit 3b8949afe9
2022-12-05 10:36:45 +01:00
c2437b51cf
smaller code-style fixes
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2022-12-05 09:35:33 +01:00
3b8949afe9
core: move configuration of polling mode to parse()
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2022-12-05 09:35:32 +01:00
09af6d9e88
refactor Core::configure() to Core::parse()
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2022-12-05 09:35:32 +01:00
14c7e57a8a
fix parsing of IP parameters
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2022-12-05 09:35:32 +01:00
Niklas Eiling
bac0b7309a
add card config option "polling" to configure polling mode in IP cores; add json parsing of hwdef to dma IP core to replace hardcoded DMA settings.
2022-11-11 04:53:58 -05:00
2a068ec3a6
core: avoid reversing initialization order list
2022-10-28 11:32:18 -04:00
0e0197a3be
fix coding style
2022-10-28 08:03:57 -04:00
9ef01d068e
update year in copyright notices
2022-08-30 12:22:40 -04:00
fb824a82f9
cleanup of comments
2022-08-30 12:21:46 -04:00
5c68a22ffe
add new IP core for standard Xilinx Aurora cores
2022-08-30 12:21:46 -04:00
49572d0a74
adapt to new plugin registry
2022-03-04 03:33:07 -05:00
8ec16094f2
fix code-style
2020-07-27 16:48:53 +02:00
74f55fa98c
refactor: more code-style improvements
2020-06-15 21:08:49 +02:00
a9f9dc4a37
refactor: no namespace scoeps in source files
2020-06-14 22:11:26 +02:00
8b7bbe27c6
refactor: whitespaces for references
2020-06-14 22:03:50 +02:00
6b3164dd26
refactor IpNode and IpCore class names
2020-06-12 00:05:03 +02:00
