Set speed of 1G for silicon only and run at 100Mbps on emulation platforms.
CRL_APB register configuration to 1000Mbps is also only required for silicon.
Minor comment corrections done.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Different GEM instances are present on evaluation and emulation platforms
of Zynq Ultrascale+ MPSoC.
To allow for automatic testing, select XPS_GEMx_INTR_ID based on the
PSU_<> present. Left initial definition intact for Zynq.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Modify clock config function to move all ZynqMP GEM related code inside
XPAR_<psu ethernet ip> checks. This fixes the compilation errors for Zynq
that are caused by references to GEM2/3.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Write to CRL_APB registers for clock control and enable 1G speed.
Move clock configuration to a separate function.
Update payload to jumbo size.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Read the phy idetifier register to identify whether PHY is Marvell or TI.
Add support for TI PHY sequence by writing to PHY CNTRL register and
tuning using RGMIICTL/RGMIIDCTL registers.
Access to extended registers in TI pHY is through REGCR and ADDAR registers.
ADDAR should be used to write the offset of register to be written
and then the value to be written. REGCR should indicate when ADDAR contains
register offset and when it contains register data.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
For 64 bit address, upper 32 bits should be updated in respective
TX and RX queue pointer registers. For tx, typecast with u32 should not
be there; remove it. For rx, update the correspondign register.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
BUFFNA is not an error and hence the status bit is cleared by the
driver. But the error handler callback is called with a zero error
code in this case. Correct the same.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
The existing changes done under EXTENDED_DESC_MODE should in fact
be done for arch 64. Extended mode needs additional BD words and since
there is no test for it at present, it is disabled.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Enable jumbo option and use updated API's for zynqmp.
Increase array size to support jumbo frames - these can be decreased by user if
not required.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Add an option to enable jumbo frames for zynqmp.
Add frame size and receive buffer length masks to instance so that they can
be updated dynamically with jumbo enable/disable.
Provide new API XEmacPs_GetRxFrameSize instead of XEmacPs_BdGetLength to
find frame size in case of jumbo frames or otherwise.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Added terminating descriptors for unused rx and tx queues to avoid
wrong interpretation of the data that resides in the memory location
ponited by the queue base registers.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Removed the alignment check for the adjacent BD gap as the controller
expects all the BDs are organized in linear order.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Modified to use single BD for both rx and tx for avoiding the
multiple version checks and probabaly create another example
for multiple BD processing.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
When gem is configured with pcs/pma core for
configuring the clocks it requires additional iic programming
other wise peripheral test won't work.
Don't include gem in peripheral test when configured with pcs/pma core.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
This patch modifies the extra OR operator in xemacps_bd.h code
that caused issue.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
