Update copyright year in source files and examples.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
Update copyright year in source files and examples.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
Update copyright year in source files and examples.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
Update copyright year in source files and examples.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
Update copyright year in source files and examples
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
Update copyright year in source files and examples
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
Update copyright year in source files and examples
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
Update copyright year in source files and examples
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
This patch corrects the hsize and stride alignment logic when DRE
is not enabled in the design.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Reviewed-by: Kedareswara rao Appana <appanad@xilinx.com>
- Added dynamic scaler filter selection logic
- Added indirection layer for sub-core API's (picture settings,
PIP background color, debug information)
- Fixed VDMA alignment in 1/2/4 pixel configurations
- Added example directory. Included files to be uused with
vpss example design that will be released separately
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
There are 4 filter coefficient tables available. The table to be
loaded in IP register bank is determined by the scaling ratio
Scale Up: Always use 6tap
Scale Dn: Different table selected based on scaling ratio
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
There are 4 Filter coefficient tables available. The table to be
loaded in the IP is determined by the scaling ratio
Scale Up: Always use 6tap
Scale Dn: Different table selected based on scaling ration
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Updated API name to load external coefficients to align with
vprocss
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Updated API name to load external coefficients to align with
vprocss update.
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Modify example to use the first available IPI device slot
for testing
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
When DRE is not enabled,adjust hsize and stride to memap data width on write channel(S2MM).
On read channel(mm2s), adjust hsize to stream data width and stride to memap data width.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies the test_app tcl file so that polled,
interrupt tests are removed from the peripheral tests.
Since we dont know whether peripherals are connected to
SPIPS or not.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies the test_app tcl file so that polled,
interrupt tests are removed from the peripheral tests.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch updates the Xil_SetTlbAttributes to mark the BD memory region
only uncaheable and updated the cache flush/invalidate api's for a53 case.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked by: Anirudha Sarangi <anirudh@xilinx.com>
-Updated driver structure, variable and API names to align with
defined coding guidelines
-Load scalers and chroma resampler coefficients only if the
instantiated configuration supports it
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
Coefficient register base address offset changed in IP from
0x400 to 0x800 to accomodate all supported taps.
Split Phase and Coefficient programming logic in 2 independent
API's. For Bicubic and Bilinear scalers only Phase needs to
be programmed.
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
Coefficient register base address offset changed in IP from 0x400 to
0x800 to accomodate all supported taps.
Split Phase and Coefficient programming logic in 2 independent
API's. For Bicubic and Bilinear scalers only Phase needs to be
programmed.
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
Added enumeration for supported resampling algorithms.
Coefficients needs to be programmed only for FIR mode. Bounded
coefficient programmin API with required condition.
Updated debug API to report resampler type and associated
coefficients
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
Added enumerations to describe supported resampling algorithms
Only FIR mode needs the programmable coeffiecients. Bounded the
coefficient programming API with the required condition.
Also updated debug API to report out the resampling type and
associated coefficients
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
IP bus name prefix changed from "AXILITES" to "CTRL" to align
with all other HLS IP's in video processing subsystem. Generated
driver updated.
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
This patch updates the iomodule tcl to handle, if iomodule doesn't
have interrupts enabled and also updates the canonical defines for
iomodule GPO*,INTC_LEVEL_EDGE,INTC_POSITIVE.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Reviewed-by: Kedareswara rao Appana <appanad@xilinx.com>
This patch fixes the wrong ifdef in the example.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
This patch updates the Xil_SetTlbAttributes
to mark the BD memory region only uncaheable and
updated the cache flush/invalidate api's for a53 case.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
In a53 processor the Cache flush api does both fulsh and invalidate
of the memory once the dma transfer is done before checking the
data we shouldn't invalidate the memory unlike the a9/microblaze case.
This patch updates the axidma examples for the same.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
In a53 processor the Cache flush api does both fulsh and invalidate
of the memory once the dma transfer is done before checking the
data we shouldn't invalidate the memory unlike the a9/microblaze case
this patch updates the axicdma examples for the same.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Should be called from application instead.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
This patch modifies the makefile by removing the unnecessary
compiler checks. With the latest compiler names, this check
is not required.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
Acked By: Sadanand Mutyala <sadanan@xilinx.com>
With the 64-bit support a new filed got added to the buffer
descriptor the number of words in a buffer desctipor
should be changed accordingly. This patch updates the same.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked by: Anirudha Sarangi <anirudh@xilinx.com>
