This patch modifies assembly level barrier function definitions
in xpseudo_asm_iccarm.h for iar compiler to fix the compilation
error for coresight driver
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-By: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
It is observed that when the C stack in put in TCM, ECC errors
get reported resulting in data abort.
This patch disables TCM ECC check temporarily before we come
to a proper conclusion regarding how to handle this use case.
Since we expect users to run code in R5 TCM, this patch removed
ECC check for TCMs to avoid data aborts.
Signed-off-by: Anirudha Sarangi <anirudh@xilinx.com>
Acked by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies xpseudo_asm_iccarm.h to fix the compilation
when dsb, isb and dmb is used by modifying for correct
function definitions
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies mpu settings in Init_MPU to truncate the
DDR size to 2Gb when DDR located at 0x0 is greater than 2GB
in the hdf
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patches modifies translation_table.S for 32bit and 64bit
BSP to limit the DDR size to 2GB if hdf contains DDR greater than
2GB size at 0x0 to comply with the specifications.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies Init_MPU API in mpu.c for mpu region
to be configured for DDR, only when it is present. It will mark
the region only for TCMs in case of DDRless system
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies translation table for a53 bsp 32bit and 64bit
to mark memory reserved in case of ddrless system
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch correct the interrupt ID's of TTC which
will be used by TEST APP.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This patch add PSU definitions for TEST APP in
xparameters_ps.h file for a53 (32,64 bit) and r5.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
This patch removes floating point flags from 32bit bsp makefile
as floating point unit is disabled in bsp for now
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies standalone bsp tcl to generate 32bit/64bit
a53 bsp by keeping compiler check in the tcl to copy the
appropriate source file while generating standalone bsp
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
UPPER_32_BITS(x) macro to handle shifts that may be >= the width of
the data type.
LOWER_32_BITS(x) macro to handle masking of 32-bit data types.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch adds various memory attribute definition
which can be used along with xil_settlbattributes API to
mark certain memory region with required attributes
such as cacheable or non-cacheable, inner/outer/non shareable
or executable or not etc.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch inclues memory attributes like device memory and
write through cacheable memory attributes to memory
attribute index register in boot.S
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
Modified cortexr5/gcc/Makefile to keep a correct check of a compiler
to update ECC_FLAGS correctly.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
to update ECC_FLAGS to fix a bug introduced during new version creation
of BSP
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies xil_settlbattributes API to work with
addresses > 4GB by modifying the address masking value
appropriate for higher addresses lies beyond 4GB
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies the makefile for a53 to take the compiler and
archiver name from cpu tcl rather than fixing them.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies the makefile for r5 to take the compiler and
archiver name from cpu tcl rather than fixing them.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies xil_printf to add support for 64bit
pointer value print in case of 64bit mode. It adds support
to print 64 bit value for long integer and long hex.
It also removes unknown specifier 'D'.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies xil_mpu.c to add the API Xil_SetMPURegion
which provide the settings for a MPU region with size
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Specify the format attribute for the xil_printf() function to allow the
compiler to do printf-style checking of the format string and arguments.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Treat 'p' conversions as alias of 'x'. Strictly, not fully correct, but
better than ignoring them.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Treat 'X' conversions as alias of 'x'. Strictly, that is not fully
correct, but still better than ignoring them.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
This patch adds coresight DCC support for Zynq Ultrascale+
MP Platform by modifying stdin and stdout range options.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This patch modifies xil-crt0.S to remove Init_Uart API call
as fsbl is initializing the UART
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies xil-crt0.S to remove Init_Uart API call
as fsbl is initializing the UART
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies Xil_DCacheFlushRange, Xil_DCacheInvalidateRange
and Xil_ICacheInvalidateRange API to add support for addresses higher
than 4GB by not truncating the addresses to 32bit
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies translation_table.S to put check whether
the DDR is present or not to fix the compilation error in
case of DDR-less system
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
