This patch removes clock related PM API ids defined in pm_defs.h
under sw_services and reassigns ids in serial order.
Signed-off-by: Rohit Fule <rohitf@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
Execution state of A53 (64-bit/32-bit) is now determined based on __aarch64__ value
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
This patch adds support for FSBL running in A53 32-bit mode and
also supports handing off to A53 32-bit applications from FSBL.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
Example has been modified to support both Zynq PL eFuse and
Ultrascale eFuse. Added GPIO pins and channels to access
Master Jtag through GPIO and RSA key hash, AES's CRC value
input macros are also added.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
As GpioPs and Timers are different for Ultrascale
all the calls related to Gpio and timers are saperated
by ifdefinitions.
Added new jtag function to access efuse of Ultrascale.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
To add ultrascale's efuse functionality added GPIO pins
and GPIO channels to access master JTAG, Fpga_Flag to tell
the FPGA series, AES CRC check flag and AES CRC value, RSA key
hash to program and RSA key hash read back and control and
secure parameters in PL instance and modified IR length
macro ZYNQ_TAP_IR_LENGTH to TAP_IR_LENGTH as IR length is same for both
Zynq and Ultrasale.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
Removed redundant code by adding common API for clock
calculations.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
Modified tcl for adding macro in xparameters.h based on the
processor.As support is being added for Ultrascale and hence
supported processors are a9 and microblaze too, removed
supported peripherals option in mld.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
As in JTAG bootmode, watchdog is not initialized, avoided stopping of
watchdog in JTAG bootmode.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
This patch use --create option for armcc compiler
instead of rc option.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This patch modifies standalone bsp tcl to generate 32bit/64bit
a53 bsp by keeping compiler check in the tcl to copy the
appropriate source file while generating standalone bsp
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies the buswidth in dummy phase as
in data phase.
Signed-off-by: RamyaSree <rdarapun@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This patch added Tx/Rx flags in qspi message format
according to qspipsu driver changes.
Signed-off-by: RamyaSree <rdarapun@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
When building xilsecure with '-rR' as arguments to make causes this error:
Compiling Xilsecure Library
make[1]: *** No rule to make target 'xsecure_sha.o', needed by 'libxilsecure.a'. Stop.
Makefile:27: recipe for target 'psu_cortexa53_0/libsrc/xilsecure_v1_0/src/make.libs' failed
make: *** [psu_cortexa53_0/libsrc/xilsecure_v1_0/src/make.libs] Error 2
Fixing this by adding a pattern rules matching the required object files.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Bhavik Ameta <bameta@xilinx.com>
This patch modifies openamp rpc_demo application to
remove the hardcoded shared memory region and support for the
memory region configuration as per requirement of the code
in MPU region settings
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies openamp echo_test application to
remove the hardcoded shared memory region and support for the
memory region configuration as per requirement of the code
in MPU region settings
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies openamp matrix_multiply application to
remove the hardcoded shared memory region and support for the
memory region configuration as per requirement of the code
in MPU region settings
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
UPPER_32_BITS(x) macro to handle shifts that may be >= the width of
the data type.
LOWER_32_BITS(x) macro to handle masking of 32-bit data types.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch adds various memory attribute definition
which can be used along with xil_settlbattributes API to
mark certain memory region with required attributes
such as cacheable or non-cacheable, inner/outer/non shareable
or executable or not etc.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch inclues memory attributes like device memory and
write through cacheable memory attributes to memory
attribute index register in boot.S
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
When building xilffs with '-rR' as arguments to make causes this error:
Compiling XilFFs Library
gmake[2]: *** No rule to make target 'ff.o', needed by 'libxilffs.a'. Stop.
Makefile:27: recipe for target 'psu_cortexa53_0/libsrc/xilffs_v3_1/src/make.libs' failed
gmake[1]: *** [psu_cortexa53_0/libsrc/xilffs_v3_1/src/make.libs] Error 2
Fixing this by adding a pattern rules matching the required object files.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
-GpuPP now has its own PmSlave derived structure and the FSM
(new structure is added because there is no peripheral with
exactly the same behavior - Usbs have also their own power island,
but compared to them GpuPPs do not have wake-up capabilities
through GIC Proxy, and GpuPPs depend on FPD while LPD is
considered always-on)
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Tested-by: Rohit Fule <rohitf@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
The ROM handlers and hooks have a different signature.
Fixes: aea3444396c3 'ROM interface: Add ROM hook table'
Cc: Kristopher Bechamp <kristop@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
XpbrPwrUpFpdHandler used to not always return XST_SUCCESS, this
problem no longer exists hence the workaround can be dropped.
Signed-off-by: Davorin Mista <davorin.mista@aggios.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-Added PLL nodes (PLLs are PM slaves)
-Implemented PLL's FSM in pm_pll.h/c
-Added PmRequirement structures for APU and RPU_0, both can request
any PLL for usage
-Implemented saving of FPD PLLs' context and powering down FPD PLLs
before FPD gets powered down (this is PLL suspend)
-Implemented restoring of PLL states when PLL is needed for usage
if FPD has been powered down (this is PLL resume)
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-Added array of CRF_APB module's register address/value pairs used
for saving/restoring CRF_APB register contents (excluding PLL
registers - PLLs have their own logic for save/restore)
-Added saving context of CRF_APB registers before FPD is powered
down and restoring saved context after FPD is powered up
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-Added PM_CAP_POWER as generic capability (defined in pm_defs).
-Slaves' FSMs should define PM_CAP_POWER capability in states which
require power parent to be ON before the state is entered. This
capability has no effect if slave node does not have power parent
-Powering up parent of a slave is done automatically by the
framework before the FSM of a slave is triggered to change the
state (slave's FSM should assume all prerequisites regarding power
are configured before FSM is triggered)
-Added PM_CAP_POWER capability in ON state of standard fsm (used for
SATA)
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-There was a bug in pmu-fw/pm binding through IPIs, because of
which in case of multiple IPI interrupts generated simultaneously
only first interrupt was handled, other interrupts were lost
-The bug existed because PM handles one request in each
XPfw_PmIpiHandler invocation, and pmu-fw clears all bitfields
in ISR register after PM handles request. Therefore, if multiple
bits were set in ISR register (simultaneous IPI interrupts), only
first one was handled and other bits were just cleared
-XPfw_PmIpiHandler now returns status and through an argument
pointer an IPI mask of master whose request has been handled
-In xpfw_user_startup.c/PmIpiHandler, return of XPfw_PmIpiHandler
is checked. If PM successfully handled IPI, only the bitfield of
master whose request is handled is set (only that IPI interrupt
is cleared). If something went wrong in PmIpiHandler/IPI0 case,
we clear all bits set in ISR register, to avoid system hanging on
this interrupt handler
-In pm_master, a check whether the master owns given mask was
performed by using '==' instead '&'. Therefore, when 2 masters
generated interrupt at the same time, PM function that checks
whether the IPI is PM related returned that the ISR value does
not match any master. This bug is fixed
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-Replaced PM defined macro definitions with macros defined in
lpd_slcr.h
-Other macros that are defined in pm_slave.h do not exist as is,
therefore are still used
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-Added macros in pm_defs.h for system shutdown argument 'restart'
-Exposed array of all masters needed to initiate their suspend upon
receiving of system shutdown call
-Added checking for restart argument of system shutdown call in pm_api.c
-Implemented PmSystemShutdown for argument restart=0 (shutdown)
-Further improvement in PmSystemShutdown depend on timeout implementation
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Signed-off-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-Every master has unique bitfield in all IPI registers
-PMU power management accesses status, trigger and enable registers
for a master using the unique master's ipiMask now
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
Move the tracking of suspend requests into the corresponding master
structures.
This patch limits the number of possible requestors to 1.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-Added structure PmSuspendRequest for tracking suspend request
related informations: which master is allowed to request whose
suspend, has the request been made, etc.
-Added functions in pm_master for handling requests
-Added calls in pm_proc for triggering acknowledge once primary
processor goes to sleep
-Added sending acknowledge if target master aborts suspend
-Timeouts to be implemented
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-Changed code in PmUpdateSlave to first determine the state to be
entered
-Added function for finding the state with required capabilities
-Removed function which was finding and changing state of a slave
(not used anymore)
-Major reason for changing this code is the bug: in USB case,
when USB is already in right state and upon the set requirement
request which should be resolved to the same state (nothing to
configure, state is already configured as requested) PM
acknowledged an error, although there was no error
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
