Commit graph

1295 commits

Author SHA1 Message Date
Andrei-Liviu Simion
3b7b32fe0e dp: tx: Moved wait for PHY ready from initialization.
PHY ready check is now done immediately before initiating link
training.

In pass-through designs where the TX reference clock is derived
from the input RX clock, having no RX clock would have resulted
the TX initialization failing due to PHY ready time out.

This patch allows TX and RX to both be initialized in any
order.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Shadul Shaikh <shaduls@xilinx.com>
2015-10-19 22:31:36 +05:30
Anirudha Sarangi
cbbf0e86d7 standalone BSP: Disable TCM ECC checks in boot code
It is observed that when the C stack in put in TCM, ECC errors
get reported resulting in data abort.
This patch disables TCM ECC check temporarily before we come
to a proper conclusion regarding how to handle this use case.
Since we expect users to run code in R5 TCM, this patch removed
ECC check for TCMs to avoid data aborts.

Signed-off-by: Anirudha Sarangi <anirudh@xilinx.com>
Acked by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
2015-10-19 22:20:43 +05:30
Kinjal Pravinbhai Patel
b239d6a0db bsp: a53: asm instructions have been modified to return proper value
This patch modifies asm instruction ldr and mfcp for a53 64bit mode
to return 64bit values

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
2015-10-19 22:04:35 +05:30
Jyotheeswar Reddy
676a985bc1 pmufw:config:Skip UART initialization
FSBL configures the UART baud rate, MIOs and Clocks. UART init code in FW is
not fully functional and in some cases may interfere with settings done by FSBL.
So skip UART init in PMUFW to avoid conflicts.

Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
Acked-by: Sarat Chand Savitala <saratcha@xilinx.com>
2015-10-19 11:02:36 +05:30
VNSL Durga
743a656e2c ZDMA: Modified XZDma_CreateBDList API
Corrected destination descriptor address calculation in
XZDma_CreateBDList API.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
2015-10-19 10:52:36 +05:30
Anurag Kumar Vulisha
c04b550bca spi: added support for sst flash part in xspips_flash_intr_example.c
For sst flash parts we need to unlock global protection bits and use
bulk erase command instead of chip erase.This patch updates the same.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
2015-10-17 00:34:06 +05:30
Anurag Kumar Vulisha
3487d7ac41 spi: changed the xspips_flash_polled_example file for sst flash parts
For sst flash parts we need to unlock global protection bits and use
bulk erase command instead of chip erase.This patch updates the same.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
2015-10-17 00:32:49 +05:30
Shadul Shaikh
b505655fe0 dprxss: Instruct RX to generate HPD interrupt
This patch generates a Hot-Plug Detect (HPD) interrupt whenever RX cable
disconnect/unplug interrupt detected.

Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Acked-by: Andrei-Liviu Simion <andreis@xilinx.com>
2015-10-17 00:24:28 +05:30
Sarat Chand Savitala
c023b29bc4 sw_services:xilsecure: Fix for authentication failures
Acknowledge DMA transfer is complete by clearing DONE status.
This will make sure that the next transfer doesn’t assume DONE when it isn’t.

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
2015-10-17 00:17:42 +05:30
Harini Katakam
7b0809dbe4 emacps: Manage clock setup & rate differences between Emulation and Silicon
Set speed of 1G for silicon only and run at 100Mbps on emulation platforms.
CRL_APB register configuration to 1000Mbps is also only required for silicon.
Minor comment corrections done.

Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
2015-10-17 00:05:29 +05:30
Harini Katakam
62177f1717 emacps: Select interrupt ID in example based on instance present
Different GEM instances are present on evaluation and emulation platforms
of Zynq Ultrascale+ MPSoC.
To allow for automatic testing, select XPS_GEMx_INTR_ID based on the
PSU_<> present. Left initial definition intact for Zynq.

Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
2015-10-17 00:04:22 +05:30
RamyaSree
d29d6bdcd0 sw_apps:zynqmp_fsbl: Modified PMU Trigger logic
This patch corrects the logic used to trigger PMU_0 IPI.
Also added code to Enable PMU_0 IPI.

Signed-off-by: RamyaSree <rdarapun@xilinx.com>
Acked-by: Sarat Chand Savitala <saratcha@xilinx.com>
2015-10-16 19:47:46 +05:30
P L Sai Krishna
5594d1f3fc sdps: Added support for SD v1.0
This patch add support for SD card v1.0

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-10-16 19:30:43 +05:30
Shadul Shaikh
1e332095b8 dptxss: Added HDCP example
This patch adds HDCP example and modifies examples, readme, index
files.

Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Acked-by: Andrei Simion <andreis@xilinx.com>
2015-10-14 23:09:34 +05:30
Shadul Shaikh
47fe2ff165 dptxss: Integrated HDCP, Timer in DisplayPort Transmitter Subsystem
This patch integrates HDCP, Timer in DisplayPort TX Subsystem.

Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Acked-by: Andrei Simion <andreis@xilinx.com>
2015-10-14 23:09:34 +05:30
Shadul Shaikh
4ef87ec22c dprxss: Added HDCP example
This patch adds HDCP example and modifies examples, index, readme files.

Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Acked-by: Andrei Simion <andreis@xilinx.com>
2015-10-14 23:09:33 +05:30
Shadul Shaikh
879b09fd24 dprxss: Integrated HDCP, Timer in DisplayPort RX Subsystem
This patch integrates HDCP and Timer in DisplayPort Receiver Subsystem.

Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Acked-by: Andrei Simion <andreis@xilinx.com>
2015-10-14 23:09:31 +05:30
VNSL Durga
c1cecfadc7 ZDMA: Modified ZDMA simple transfer example
Hardcoded address for pointers are changed to arrays.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
2015-10-14 10:37:57 +05:30
VNSL Durga
5e98df225c Xilskey: Modified efuse example
Added new lines in example prints.
Modified CRC calculation API name and
provided backward compatability.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-10-12 18:56:09 +05:30
VNSL Durga
545e14f93b xilskey: Modified changelog txt
Modifications for 4.0 and 3.0 are added to changelog

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-10-12 18:56:02 +05:30
VNSL Durga
09c1374102 xilskey: Corrected error code names
Error codes names of efuse PL Ultrascale are corrected

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-10-12 18:55:54 +05:30
VNSL Durga
2af5aa5b71 xilskey: Added BBRAM Ps example
To program Bbram PS example is provided this example
doesnot require any input.h file it doesnot contain any control
bits to be programmed.
It has only one feature is to program AES key into BBRAM.
User can edit the macro XSK_ZYNQMP_BBRAMPS_AES_KEY with the key
to be programmed.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-10-12 18:55:45 +05:30
VNSL Durga
507e33c593 Xilskey: Added Example for Zynq MP efusePs
To program efuse PS of Zynq MP user has to edit input.h file
in input.h file default all will be in FALSE sate which ever has to be
programmed need to be changed to TRUE.
In example after programming cache will be reloaded and keys will be
read from cache. If user wants read API can be changed to read from
efuse memory.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-10-12 18:55:36 +05:30
VNSL Durga
b92437c68b xilskey: Added BBRAM PS functionality
Added BBRAM PS programming APIs for Zynq MP platform
In BBRAM there is no provision for saperate CRC check
CRC check can be performed only while programming AES key
So user no need to calculate CRC of key if they provide key
for programming CRC check will also be performed internally.
User can also make BBRAM key to Zero at any time.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-10-12 18:55:27 +05:30
VNSL Durga
e7aeea3a1f xilskey: cleaned library's makefile
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-10-12 18:55:19 +05:30
VNSL Durga
53ebf58e2e xilskey: Added efuseps APIs for Zynq MP
For ZynqMp platform's Efuse PS interface functions are added.
In efuse PS we can programm AES, User keys and PPK0, PPK1 hashs
SPK Id, JTAG  user code and including some control bits.
If Tbits are not programmed some programming features can't be
programme, user no need to call any API to program this Tbits
they are programmed internally when you tried to program any
of the programming bits if Tbits are not programmed on efuse.
PPK hash accepts input in the form bootgen's hash output
user no need to change HASH.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-10-12 18:55:10 +05:30
VNSL Durga
72073f36fe xilskey: Added Xilskey write and read regs APIs
Modified CRC calculation API to calculate CRC of
ZynqMP efuse PS's AES CRC.
Added Ceil function to calculate ceil.
Added write and read registers APIs.
Modified Xilskey_CrcCalculation API to
XilSKey_CrcCalculation

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-10-12 18:55:00 +05:30
VNSL Durga
66a63c151b xilskey: Provided conditional compilation
To support Zynq MP platform conditional compilation
is provided.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-10-12 18:54:49 +05:30
VNSL Durga
f8ed126215 xilskey: Added efuse PS and bbram PS support
Added dependencies.props file is addded to pick required
.h file for selected example file.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-10-12 18:52:20 +05:30
Harini Katakam
05efa29697 lwip: Add support for TI phy
Change the initialization, TX/RX tuning and auto negotiation sequence
as per TI phy spec.

Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
2015-10-12 18:30:40 +05:30
Harini Katakam
ed027bf4b9 qspipsu: Increase setup and hold time
Increase the setup and hold time of qspi to accomodate for a worst case
of ~15ns with ref clk of 300MHz.

Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
2015-10-12 18:21:47 +05:30
Kinjal Pravinbhai Patel
3c80ca4b5b sw_apps: updated openamp rpc demo description for zynq support
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
2015-10-12 18:21:31 +05:30
Kinjal Pravinbhai Patel
fe5cf411ba sw_apps: updated openamp matrix multiply description for zynq support
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
2015-10-12 18:21:20 +05:30
Kinjal Pravinbhai Patel
50e5bc791b sw_apps: updated openamp echo test description for zynq support
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
2015-10-12 18:21:06 +05:30
Rohit Consul
33835aa8dc v_hdmitx: Add initial version of hdmi tx core driver
Added hdmi tx core driver v1.0 (on behalf of Gilbert Magnaye)

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-10-12 16:29:53 +05:30
Rohit Consul
a42863ac75 v_hdmirx: Add initial version of hdmi rx core driver
Added hdmi rx core driver v1.0 (on behalf of gilbert magnaye)

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-10-12 16:29:43 +05:30
Rohit Consul
a6f402d225 v_hdmitxss: Add initial version of hdmi tx subsystem driver
Added hdmi tx subsystem driver v1.0 (on behalf of Gilbert
Magnaye)

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-10-12 16:29:33 +05:30
Rohit Consul
3713b27d5a v_hdmirxss: Add initial version of hdmi rx subsystem driver
Add initial revision of hdmi rx subsystem driver

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-10-12 16:28:58 +05:30
P L Sai Krishna
ce8d105a07 xilopenamp: Corrected the Makefile for IAR.
This patch modifies the Makefile of xilopenamp to
remove the compilation error for IAR compiler.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
2015-10-12 13:09:11 +05:30
P L Sai Krishna
a285a07ea5 xilsecure: Corrected Makefile error for IAR.
This patch modifies the Makefile of xilsecure to
remove the compilation errors for IAR compiler.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
2015-10-12 13:09:03 +05:30
P L Sai Krishna
9b24ae0a67 xilisf: Corrected the Makefile error for IAR.
This patch modifies the Makefile of xilisf to
remove the compilation errors for IAR compiler.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
2015-10-12 13:08:54 +05:30
P L Sai Krishna
07a30bad5b xilflash: Corrected the Makefile error for IAR.
This patch modifies the xilflash Makefile to
remove the compilation error for IAR compiler.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
2015-10-12 13:08:43 +05:30
P L Sai Krishna
2e94f1a88e xilffs: Corrected Makefile error for IAR.
This patch modifies the make file of xilffs to
remove the compilation error for IAR compiler.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
2015-10-12 13:08:14 +05:30
Shadul Shaikh
1917c9d19e dptxss: Added index.html file
This patch adds index.html file in examples folder

Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Acked-by: Andrei-Liviu Simion <andreis@xilinx.com>
2015-10-12 10:56:48 +05:30
Shadul Shaikh
c55f4acbc2 dptxss: Added custom resolution support
This patch adds custom resolution support and wrapper function
for setting a redriver path.

Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Acked-by: Andrei-Liviu Simion <andreis@xilinx.com>
2015-10-12 10:56:18 +05:30
VNSL Durga
f421c75450 Xilskey: Modified JtagWrite API
According to IEEE 1149.1 programming will start after
TCK toggle at higher edge of clock and will be ended at
RTI state change and followed TCK toggle.
So JtagWrite API is modified accordingly.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-10-12 10:46:24 +05:30
VNSL Durga
601ba781fb xilskey: Added DFT control bits programming
DFT JTAG disable and DFT mode disable control bits
programming and reading from status register are added
to efuse example and also input macros in xilskey_input.h
file.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-10-12 10:46:13 +05:30
VNSL Durga
1553beac28 xilskey: Added DFT control bits
DFT control bits of efusePS for Zynq Platform is
added.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-10-12 10:46:01 +05:30
VNSL Durga
41169b9bfd xilskey: Added new version
Support for programming DFT bits is provided.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-10-12 10:45:31 +05:30
Rohit Consul
86f6445653 v_tpg: Bug fix for vidout lock monitor read mechanism
Fixed the read API for video lock monitor to read from
peripheral. Update example design to align with example design
update in hw

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-10-12 10:45:15 +05:30