8ec16094f2
fix code-style
2020-07-27 16:48:53 +02:00
e5545aa17e
emc: add initial code to flash FPGA bitstream via PCIe
2020-07-08 17:16:43 +02:00
08114652d6
emc: add stub IP
2020-07-08 15:20:05 +02:00
Hatim Kanchwala
8a4e95d75c
Use sensible colour scheme for error status output
2020-07-04 15:11:01 +02:00
6c225c8fae
update VILLAScommon submodule
2020-06-15 21:21:05 +02:00
74f55fa98c
refactor: more code-style improvements
2020-06-15 21:08:49 +02:00
a9f9dc4a37
refactor: no namespace scoeps in source files
2020-06-14 22:11:26 +02:00
8b7bbe27c6
refactor: whitespaces for references
2020-06-14 22:03:50 +02:00
6b3164dd26
refactor IpNode and IpCore class names
2020-06-12 00:05:03 +02:00
7c92a30ab4
several cleanups and bugfixes
2020-06-11 23:55:05 +02:00
b7e5bfead2
harmonize codestyle
2020-06-11 18:38:46 +02:00
77b55f65f7
use new plugin mechanism
2020-06-11 18:19:03 +02:00
86f8997b05
gpio: add new IP for AXI programmable GPIO
2020-06-11 15:58:02 +02:00
d5b1012b75
intc: fix name of register space
2020-06-11 15:57:05 +02:00
c906116d86
update to latest VILLAScommon submodule
2020-06-11 14:20:33 +02:00
3b28eea7d2
aurora_axis: add two functions to reset counters and configure loopback mode
2020-06-11 13:08:42 +02:00
1596208bb6
aurora_axis: dump frame counters
2020-06-11 13:01:44 +02:00
3d15323376
aurora_axis: harmonize with HDL changes
2020-06-11 13:01:27 +02:00
Hatim Kanchwala
448068082f
Improve comments for status/control register bits
2020-06-08 00:55:33 +02:00
Hatim Kanchwala
0a7c6cc31c
Define register addresses and bits
2020-06-05 23:41:08 +02:00
Hatim Kanchwala
bf67a2e5f0
Add initial Aurora driver
2020-06-02 00:54:31 +02:00
f6a78bea69
dma: add dump() method
2019-08-15 13:54:58 +02:00
Hatim Kanchwala
bf74db8e79
Debug update
2019-06-24 12:11:44 -04:00
8b45a8bcac
fix include paths
2018-08-21 14:25:20 +02:00
2112038d70
Merge branch 'feature/hls-rtds2gpu' into develop
2018-08-21 13:51:32 +02:00
df89b63368
fix include paths
2018-08-21 11:07:53 +02:00
63a1eb2f7f
remove some obsolete C code files
2018-06-25 17:22:31 +02:00
7409d2024d
add more copyright / license headers
2018-06-25 17:03:09 +02:00
7fd6599ea6
update copyright years
2018-06-25 15:33:14 +02:00
Daniel Krebs
d853d5e0d3
wip GPU RTT
2018-06-06 09:55:14 +02:00
Daniel Krebs
f413712b86
gpu2rtds: unit test working
2018-06-04 17:36:36 +02:00
Daniel Krebs
93fe1390d6
fix wrong usage of reinterpret_cast in ips and tests
2018-06-04 17:36:36 +02:00
Daniel Krebs
010e0c3681
hls: add base HLS IP and enable virtual multi-inheritance
...
Virtual inheritance is required because (for example) the Rtds2Gpu
IP inherits from Hls and IpNode who both inherit from IpCore.
2018-06-04 17:36:36 +02:00
Daniel Krebs
28458fdf8a
update rtds2gpu HLS IP to v1.1
...
- better tested IP (testbenches)
- detect invalid frame sizes
- more status reporting
2018-06-04 17:36:15 +02:00
Daniel Krebs
bf286568dd
rtds2gpu IP works
2018-06-04 17:36:15 +02:00
Daniel Krebs
00fb0363dd
ips/switch: add more sanity checks for making connections
2018-06-04 17:30:11 +02:00
Daniel Krebs
e9add5d602
ips/dma: enable interrupts by default
2018-06-04 14:20:06 +02:00
Daniel Krebs
28143e7188
ips/rtds: add C++ version of RTDS IP
2018-06-04 14:20:06 +02:00
Daniel Krebs
8e63785073
ips/dma: change interface, get byte count from {read,write}Complete()
2018-06-04 14:20:06 +02:00
Daniel Krebs
2e339b406d
lib/ips: add data fifo IP needed for stream routing
2018-06-04 14:20:06 +02:00
Daniel Krebs
a0c5acce4c
ip-node: implement connect interface and update AxiStreamSwitch implementation
2018-06-04 14:20:06 +02:00
Daniel Krebs
5097827757
fix include paths, use <villas/...> style
2018-06-04 13:24:57 +02:00
Daniel Krebs
7dcdfaccd9
ips/dma: let user deal with making memory accessible to DMA
...
It is probably too costly to do (and verify) it on every read
or write. Furthermore, the user knows better how to make a certain
memory available to the DMA.
2018-05-15 18:04:24 +02:00
Daniel Krebs
f644a9faa8
ips/pcie: move BAR0 mapping from card into PCIe IP
2018-05-15 18:04:24 +02:00
Daniel Krebs
89b5169a6e
ips/pcie: parse AXI/PCI BARs and create mappings to/from PCIe address space
...
This is used for translations that don't use VFIO which used to bridge
the PCIe address space by creating direct mappings from process VA to
the FPGA. When we want to communicate directly via PCIe without the
involvment of the CPU/VFIO, we need the proper translations that are
configured in the FPGA hardware.
2018-05-15 18:04:24 +02:00
Daniel Krebs
8f3833bc73
ips/dma: rename pingpong to memcpy and always connect loopback
2018-05-15 18:04:24 +02:00
Daniel Krebs
3e505c74bf
ips/bram: add block RAM IP and use it with DMA test
2018-04-13 15:35:41 +02:00
Daniel Krebs
507ea77ad6
ips/dma: add (simple) DMA driver
2018-03-26 16:17:26 +02:00
Daniel Krebs
4f6694420f
lib: remove old and unused C files
2018-03-26 16:17:26 +02:00
Daniel Krebs
60882f1086
lib/memory: implement memory handling with allocators and blocks
...
This commit is 2/2 of a series of patches and not working on its own.
2018-03-26 16:17:20 +02:00
