This patch modifies the order of execution in training pattern 1 callback as
DP159 programming for training pattern 1 and then link bandwidth callback.
This modification require for few GPUs (Intel) to allow DP159 programming for
training pattern 1 before link bandwidth callback.
Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
To allow for automatic testing, select IIC_INTR_ID based on the
PSU_<> present. Left initial definition intact for Zynq.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This patch modifies modification history of DisplayPort TX Subsystem driver
example files.
Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
In Stream reporting API if custom tag is detected print stream
properties as-is instead of using the mode table based API's
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This patch enables rtc controller to switch to battery
when vcc_psaux is not available.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
Reviewed-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Renamed XV_HdmiTxSs_SendAudioInfoFrame API to
XV_HdmiTxSs_SendAuxInfoFrame
Corrected Ppc data type to XVidC_PixelsPerClock
Removed vtc patch as fix is available in vtc driver v7.1
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Updated pixel per clock parameter type to reflect usage
Deleted hdcp timer calls from - not needed in this module
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Polled for Transfer Complete bit after sending CMD6
in case of eMMC card. since CMD6 expects a R1b response
we need to check for Transfer complete before sending
next command.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Added new interlaced source select field to provide interlaced programming option to user.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
This patch does following things:
Added polling for transfer complete for cmd6 in case
of eMMC and MMC card.
Added 2.0 controller version check in case of eMMC to
switch for High speed mode in Zynq.
Added check for eMMC card, since HS200 mode switching
will only support by eMMC.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Acked-by: Harini Katakam <harinik@xilinx.com>
Few IP parameters exported in smaller cases to the hdf
but the dirver tcl is checking for the same parameters in
upper case resulting wrong values are being genearted
in xparameters.h file. This patch fixes this issue.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Created a new vesrion of can can_v3_1
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Video PHY driver for abstraction of GTs.
Contribution from Gilbert Magnaye on HDMI.
Contribution from Vamsi Krishna Dhanikonda on DisplayPort.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Rohit Consul <rohitco@xilinx.com>
Compilation failure if an HDCP design was generated without a
timer counter instatiated.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Shadul Shaikh <shaduls@xilinx.com>
PHY ready check is now done immediately before initiating link
training.
In pass-through designs where the TX reference clock is derived
from the input RX clock, having no RX clock would have resulted
the TX initialization failing due to PHY ready time out.
This patch allows TX and RX to both be initialized in any
order.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Shadul Shaikh <shaduls@xilinx.com>
For sst flash parts we need to unlock global protection bits and use
bulk erase command instead of chip erase.This patch updates the same.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
For sst flash parts we need to unlock global protection bits and use
bulk erase command instead of chip erase.This patch updates the same.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Set speed of 1G for silicon only and run at 100Mbps on emulation platforms.
CRL_APB register configuration to 1000Mbps is also only required for silicon.
Minor comment corrections done.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Different GEM instances are present on evaluation and emulation platforms
of Zynq Ultrascale+ MPSoC.
To allow for automatic testing, select XPS_GEMx_INTR_ID based on the
PSU_<> present. Left initial definition intact for Zynq.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
This patch adds HDCP example and modifies examples, readme, index
files.
Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Acked-by: Andrei Simion <andreis@xilinx.com>
This patch adds HDCP example and modifies examples, index, readme files.
Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Acked-by: Andrei Simion <andreis@xilinx.com>
