This patch modifies asm_vectors.s and xil_exception.c to print the
address for instruction causing data abort and prefetch abort in
default handler
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies Xil_DCacheInvalidateRange and Xil_DCacheFlushRange
to remove unnecessary dsb in the APIs. It also adds necessary
Xil_L2CacheSync in Xil_L2CacheInvalidateRange API.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch changes the initialization order in boot.S to follow
the correct order as specified in CortexA9 TRM
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies standalone.tcl, A53 gcc makefile and
R5 gcc makefile such that profiling support for these
A53/R5 bsps was removed.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This patch modifies standalone.tcl for supporting psu_microblaze
and also pss_* notation was replaced to psu_*.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This patch modifies the function signature of lseek
to compile on ICC ARM compiler.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This patch modifies uartns550 peripheral name from
axi_uartns550 to axi_uart16550.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This patch changes the IP names in the range property for
uartlite and uartns550 to axi_uartlite and axi_uartns550.
Signed-off-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch reverts back the function signature in a53,a9 and
r5 xil_printf API.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This patch updates the standalone files copyright information with the
latest content.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This patch modifies xpm_counter file. Removed old notation uint32 and used u32.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
Modified boot code to enable scu after MMU is enabled and
removed incorrect initialization of TLB lockdown register in
gcc/boot.S & cpu_init.S, armcc/boot.S and iccarm/boot.s
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies cortex-a9 L2CacheInvalidate API for calculating stack
region and flushing out to memory before cache invalidation. This safeguards link
register value in stack from being corrupted due to cache invalidation.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This patch includes the xil_types.h in missing header files like xil_assert.h,sleep.h, xil_testcache.h and xpseudo_asm_gcc.h.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This patch modified .mld that is required for the
unifing process of standalone code.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This patch unifies standalone for both Zynq and ZynqMP
platforms. Also follows misrac guidelines.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This patch fixes the xilkernel_thread_demo app compilation error
when microblaze is configured with mmu(C_USE_MMU) greater than one.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
This patch modifies translation table entries in armcc/translation_table.s and
iccarm/translation_table.s to fix the compilation error
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies translation table entries for cortexa9 in armcc/translation_table.s,
gcc/translation_table.s and iccarm/translation_table.s to match with the address map of
zynq
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Do not use r16 to pass arguments to mcount
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
Do not use r16 to pass arguments to mcount
Signed-off-by: Subbaraya Sundeep Bhatta <sbhatta@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
