The axiethernet ip contains 3 inbuilt blocks init
--> Axi Ethernet MAC
--> Axi Etherent BUF
--> PCS/PMA Core
During the vivado version < 2015.2 the axiethernet ip
being exported to hdf in flat mode and the hsi opens this in flat mode.
But from 2015.3 build onwards the axiethernet ip is tagged as core in the vivado
and hsi will open the ip in hier IP mode(hierarchy) means for user only
top level axiethernet instance will be visible and it will contains all
the properties related to the sub-cores.
In order to allow backward compatabilty
---> If a xml/hdf file which got created with the vivado version < 2015.3 being exported to
the sdk >= 2015.3.
---> Two drivers will be active to resolve this issue.
---> axiethernet_v4_4 will be attached to BUF this will fix the backward compatabilty issue.
---> axiethernet_v5_0 will be attached to top level block for newer features.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
This patch removes NULL pointer checks for Rx/Tx
buffers since writing/reading from 0x0 is permitted.
Used Tx/Rx flags to check for Writing/reading.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
The current timeout value is not enough for erase operation on slower
devices. so increasing the timeout value and also added usleep for
timeout routine to have a precise timeout.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
This patch add support for Macronix 512Mb flash and
corrected the if condition logic, by replacing equal-to
operator with equality operator.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch modifies the if condition logic for ReadId
function in examples by replacing equal-to operator
with equality.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch modifies the Bus width value during dummy phase
in examples since it is recommended to be same as in
data phase.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Underlying subcores now use model parameters to get the static
configuration. Update the subsystem drivers to use this
information. Also user defined scaler cofficient table is moved
to application code
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Updated tcl file to include model parameters. Also updated the
code to use new parameters instead of hard-coded values defined
earlier
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Updated the tcl and mdd files to define model parameters. Updated
the code to use new parameters instead of hard-coded values
defined earlier
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Updated the tcl and mdd files to define model parameters.
Updated the code to use new parameters instead of hard-coded
values defined earlier
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Updated the tcl and mdd files to define model parameters.
Updated the code to use new parameters instead of hard-coded
values defined earlier
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Updated the tcl and mdd files to define model parameters.
Updated the code to use new parameters instead of hard-coded
values defined earlier
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Updated the tcl and mdd files to define model parameters.
Updated the code to use new parameters instead of hard-coded
values defined earlier
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Updated the tcl and mdd files to define model parameters.
Updated the code to use new parameters instead of hard-coded
values defined earlier
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Video processing subsystem driver is added to the repo. This
driver currently is associated with a non-HIP version of the
IP. No makefile available. Hard-coded g.c file used, but not
included.
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
HLS generated Layer 1 driver for csc core along with
manually written layer 2. Pending update of driver tcl
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Compiler flags for psu_microblaze BSP, based on HW IP parameters, are not being generated by HSI. This is being done for normal microblaze by an unknown entity in the build flow and the same is being figured out. However the same flags can be generated by using cpu tcl and this work-around is implemented here.
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
PMU Microblaze related parameters are generated into xparameters.h based on the IP parameters.
This tcl generates parameters with prefix XPAR_MICROBLAZE so that they can be used with generic microblaze bsp/drivers.
Clock frequency param is also generated based on C_FREQ param of psu_microblaze IP.
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
This patch modifies the SPI flash examples to support for
Zynq Ultrascale MPSoC. In zynq we are selecting the hardware
using chip select 0 where as in Zynq Ultrscale MPSoC we have
to use chip select 1 to select the hardware and we are using
different interrupt id's for Zynq and Zynq Ultrascale MPSoC.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch updated the canfd Data swaping issue and updated the
AFRID and AFRMASK offsets to correct values.
Signed-off-by: naga sureshkumar relli <nagasure@xilinx.com>
