This patch updates the register offsets in the AXI4 data path
as per latest IP version(v4.1).
The addresses are changed to accommodate increased data width.
With old address map and increased data width user had to generate AXI4 unaligned transactions.
Therefore, the address map was changed for ease of use in the IP.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
This does following things
1. For lees than 8 byte requests, done in IO mode.
2. One dummy GenFifo entry at the end in case of IO mode.
3. used memcpy while filling TxFifo.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
The recommendation from design is to have bus width of dummy entry =
bus width of address phase (whether this is 1, 2 or 4).
This code will remain same irrespective of QEMU. Hence change the comment.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Driverwide, scripted change to convert 3-line
comments to single line comments.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
Driverwide, scripted change to convert 3-line comments
to single line comments.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This patch does following things.
1. Added Cache support.
2. Modified TXD_DEPTH to 64.
3. Enabled RXEMPTY interrupt.
4. Modified the param passed to XQspiPsu_ReadRxFifo API to
RxThreshold*4, since it is expecting number of bytes to read.
5. Used Qspipsu Instance buffers in Interrupt handler rather
than Msg buffers.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch removes the status register bit definations
that are not available on the RTL.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
Removed the configuration of DMA Buffer Boundary register in WriteSpareBytes API
as the driver uses oob size as pkt size and thus configuring DMA Buffer
Boundary Register has no effect.
Signed-off-by: Shakti Bhatnagar <shaktib@xilinx.com>
Since the check for the block to have reached the end block was at the end of the loop,
thus assert call triggering could happen if the block crosses the max block limit,
making the driver to hang. Thus to fix the triggering of assert call,
the check for the block to have reached the max block is being done at the start of
the loop in XNandPsu_CalculateLength function.
The u32 typecasting for the variable OffsetVar has been removed and the data type for
the variable TempLen has been changed to u64 as for higher block numbers the value for
these variables will require u64 datatype otherwise corrupted value will get stored
which will lead to wrong calculation of block.
Signed-off-by: Shakti Bhatnagar <shaktib@xilinx.com>
Removed the workaround for qemu in driver code as qemu now supports
ecc and bad block table handling.
Signed-off-by: Shakti Bhatnagar <shaktib@xilinx.com>
Modified the number of bytes of data to be read for signature and version when
NO OOB option is enabled.
Signed-off-by: Shakti Bhatnagar <shaktib@xilinx.com>
Modified number of bytes to be read for bbt in oob and bbt with signature
and version for no oob option. This change is done kept in mind that it
should support flashes with small page size as well.
Signed-off-by: Shakti Bhatnagar <shaktib@xilinx.com>
Setting BBT option at the beginning and checking afterwards to set
the offset for signature and version.
Signed-off-by: Shakti Bhatnagar <shaktib@xilinx.com>
Performing Read modify write operation for the interrupt status enable
and interrupt status register in readpage function instead of directly
writing to fix the masking error interrupts in case ecc enabled.
Signed-off-by: Shakti Bhatnagar <shaktib@xilinx.com>
If oob size is less than 64 bytes, ecc position should start from 0 position
of oob area, else should be at the end of the oob area.
Keeping ecc start position in alligned with the Linux nand base ecc layout.
Signed-off-by: Shakti Bhatnagar <shaktib@xilinx.com>
QSPI HW doesn't actually care what the SPI mode is for the dummy phase
of flash commands. We have confirmed this with randomized testing.
However due to a core limitation of QEMU it is expected to match the
mode of the address phase for QEMU.
So since QEMU is the only platform that cares, set the dummy mode to
QEMUs expectation.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
This patch modifies the eeprom page size to 32 for zynq ultrascale MP
in polled and interrupt examples.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
