This patch modifies the SPI flash examples to support for
Zynq Ultrascale MPSoC. In zynq we are selecting the hardware
using chip select 0 where as in Zynq Ultrscale MPSoC we have
to use chip select 1 to select the hardware and we are using
different interrupt id's for Zynq and Zynq Ultrascale MPSoC.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch updated the canfd Data swaping issue and updated the
AFRID and AFRMASK offsets to correct values.
Signed-off-by: naga sureshkumar relli <nagasure@xilinx.com>
This patch updates the register offsets in the AXI4 data path
as per latest IP version(v4.1).
The addresses are changed to accommodate increased data width.
With old address map and increased data width user had to generate AXI4 unaligned transactions.
Therefore, the address map was changed for ease of use in the IP.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Check for card detection only if that signal is present
(based on HAS_CD macro)
Signed-off-by: Srinivas Goud <srinivas.goud@xilinx.com>
Signed-off-by: Harini Katakam <harinik@xilinx.com>
This does following things
1. For lees than 8 byte requests, done in IO mode.
2. One dummy GenFifo entry at the end in case of IO mode.
3. used memcpy while filling TxFifo.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
While creating new FSBL+BSP project, made xilsecure library
to be selected by default. This avoids compilation errors
when FSBL project is created.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
The makefile tries to detect gnu vs ARM toolchain by string-comparing
the COMPILER with some hardcoded values. This fails when the toolchain
is specified with directory components. Hence, remove directory
components from the tests.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
When authentication of partitions is not enabled, decryption is failing.
This patch fixes this issue.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
The recommendation from design is to have bus width of dummy entry =
bus width of address phase (whether this is 1, 2 or 4).
This code will remain same irrespective of QEMU. Hence change the comment.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
This patch does the changes in FSBL to match the signature changes of
few functions in xilsecure library.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
The pm_client.h headers hold processor specific information. Move common
information to the common header.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
swbeta2 commit 1b173007d1cc009bffeb2969a5a5bacc533647db
IPI0 is used by PMUFW for PM requests and the mask is used for determining
the Master. There are chances of IPIs being triggered before FW Init but
un-handled or even bits that are not cleared by ROM, causing a corruption
of the ISR mask. So PMUFW should cleanup these bits during startup
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
swbeta2 commit 572db0eb0f48b4f7f5684abea721c6fac92ccdee
When powering up the RPU island the individual RPU core resets as well
as the reset for the whole island are asserted. To ensure proper resume,
the island reset needs to be released when the island is powered up.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
